/* 
* File:    p3_events.c
* CVS:     $Id: p3_events.c,v 1.48.2.15 2006/10/05 18:51:57 terpstra Exp $
* Author:  Joseph Thomas
*          jthomas@cs.utk.edu
* Mods:    <your name here>
*          <your email address>
*/

#include "papi.h"
#include "papi_internal.h"

native_event_entry_t *native_table;
hwi_search_t *preset_search_map;

/* Note:  MESI (Intel) and MOESI (AMD) bits are programmatically defined
          for those events that can support them. You can find those
          events in this file by searching for HAS_MESI or HAS_MOESI.
          Events containing all possible combinations of these bits
          can be formed by appending the proper letters to the end of
          the event name, e.g. L2_LD_MESI or L2_ST_MI. Some of these
          bit combinations are used in the preset tables. In these
          cases they are explicitly defined. Others can be defined
          as needed. Otherwise the user can access these native events
          using _papi_hwd_name_to_code() with the proper bit characters
          appended to the event name.
*/ 

/* These enumeration tables will be used to define the location
   in the native event tables.  Each even has a unique name so as
   to not interfere with location of other events in other native
   tables.  The preset tables use these enumerations to lookup
   native events.
*/
/* Pentium III enumerations */
enum {
   PNE_P3_DATA_MEM_REFS = 0x40000000,
   PNE_P3_DCU_LINES_IN,
   PNE_P3_DCU_M_LINES_IN,
   PNE_P3_DCU_M_LINES_OUT,
   PNE_P3_DCU_MISS_OUTSTANDING,
   PNE_P3_IFU_IFETCH,
   PNE_P3_IFU_IFETCH_MISS,
   PNE_P3_ITLB_MISS,
   PNE_P3_IFU_MEM_STALL,
   PNE_P3_ILD_STALL,

   PNE_P3_L2_IFETCH,
   PNE_P3_L2_LD,
   PNE_P3_L2_ST,
   PNE_P3_L2_RQSTS,

   PNE_P3_L2_LINES_IN,
   PNE_P3_L2_LINES_OUT,
   PNE_P3_L2_M_LINES_INM,
   PNE_P3_L2_M_LINES_OUTM,
   PNE_P3_L2_ADS,
   PNE_P3_L2_DBS_BUSY,
   PNE_P3_L2_DBS_BUSY_RD,
   PNE_P3_BUS_DRDY_CLOCKS_SELF,
   PNE_P3_BUS_DRDY_CLOCKS_ANY,
   PNE_P3_BUS_LOCK_CLOCKS_SELF,
   PNE_P3_BUS_LOCK_CLOCKS_ANY,
   PNE_P3_BUS_REQ_OUTSTANDING,
   PNE_P3_BUS_TRAN_BRD_SELF,
   PNE_P3_BUS_TRAN_BRD_ANY,
   PNE_P3_BUS_TRAN_RFO_SELF,
   PNE_P3_BUS_TRAN_RFO_ANY,
   PNE_P3_BUS_TRANS_WB_SELF,
   PNE_P3_BUS_TRANS_WB_ANY,
   PNE_P3_BUS_TRAN_IFETCH_SELF,
   PNE_P3_BUS_TRAN_IFETCH_ANY,
   PNE_P3_BUS_TRAN_INVAL_SELF,
   PNE_P3_BUS_TRAN_INVAL_ANY,
   PNE_P3_BUS_TRAN_PWR_SELF,
   PNE_P3_BUS_TRAN_PWR_ANY,
   PNE_P3_BUS_TRANS_P_SELF,
   PNE_P3_BUS_TRANS_P_ANY,
   PNE_P3_BUS_TRANS_IO_SELF,
   PNE_P3_BUS_TRANS_IO_ANY,
   PNE_P3_BUS_TRAN_DEF_SELF,
   PNE_P3_BUS_TRAN_DEF_ANY,
   PNE_P3_BUS_TRAN_BURST_SELF,
   PNE_P3_BUS_TRAN_BURST_ANY,
   PNE_P3_BUS_TRAN_ANY_SELF,
   PNE_P3_BUS_TRAN_ANY_ANY,
   PNE_P3_BUS_TRAN_MEM_SELF,
   PNE_P3_BUS_TRAN_MEM_ANY,
   PNE_P3_BUS_DATA_RCV,
   PNE_P3_BUS_BNR_DRV,
   PNE_P3_BUS_HIT_DRV,
   PNE_P3_BUS_HITM_DRV,
   PNE_P3_BUS_SNOOP_STALL,
   PNE_P3_FLOPS,
   PNE_P3_FP_COMP_OPS_EXE,
   PNE_P3_FP_ASSIST,
   PNE_P3_MUL,
   PNE_P3_DIV,
   PNE_P3_CYCLES_DIV_BUSY,
   PNE_P3_LD_BLOCKS,
   PNE_P3_SB_DRAINS,
   PNE_P3_MISALIGN_MEM_REF,
   PNE_P3_EMON_KNI_PREF_DISPATCHED_PREFETCH_NTA,
   PNE_P3_EMON_KNI_PREF_DISPATCHED_PREFETCH_T1,
   PNE_P3_EMON_KNI_PREF_DISPATCHED_PREFETCH_T2,
   PNE_P3_EMON_KNI_PREF_DISPATCHED_WEAKLY_ORDERED_STORES,
   PNE_P3_EMON_KNI_PREF_MISS_PREFETCH_NTA,
   PNE_P3_EMON_KNI_PREF_MISS_PREFETCH_T1,
   PNE_P3_EMON_KNI_PREF_MISS_PREFETCH_T2,
   PNE_P3_EMON_KNI_PREF_MISS_WEAKLY_ORDERED_STORES,
   PNE_P3_INST_RETIRED,
   PNE_P3_UOPS_RETIRED,
   PNE_P3_INST_DECODED,
   PNE_P3_EMON_KNI_INST_RETIRED_PACKED_AND_SCALAR,
   PNE_P3_EMON_KNI_INST_RETIRED_SCALAR,
   PNE_P3_EMON_KNI_COMP_INST_RET_PACKED_AND_SCALAR,
   PNE_P3_EMON_KNI_COMP_INST_RET_SCALAR,
   PNE_P3_HW_INT_RX,
   PNE_P3_CYCLES_INT_MASKED,
   PNE_P3_CYCLES_INT_PENDING_AND_MASKED,
   PNE_P3_BR_INST_RETIRED,
   PNE_P3_BR_MISS_PRED_RETIRED,
   PNE_P3_BR_TAKEN_RETIRED,
   PNE_P3_BR_MISS_PRED_TAKEN_RET,
   PNE_P3_BR_INST_DECODED,
   PNE_P3_BTB_MISSES,
   PNE_P3_BR_BOGUS,
   PNE_P3_BACLEARS,
   PNE_P3_RESOURCE_STALLS,
   PNE_P3_PARTIAL_RAT_STALLS,
   PNE_P3_SEGMENT_REG_LOADS,
   PNE_P3_CPU_CLK_UNHALTED,
   PNE_P3_MMX_SAT_INSTR_EXEC,
   PNE_P3_MMX_UOPS_EXEC,
   PNE_P3_MMX_INSTR_TYPE_EXEC_MUL,
   PNE_P3_MMX_INSTR_TYPE_EXEC_SHIFT,
   PNE_P3_MMX_INSTR_TYPE_EXEC_PACK_OPS,
   PNE_P3_MMX_INSTR_TYPE_EXEC_UNPACK_OPS,
   PNE_P3_MMX_INSTR_TYPE_EXEC_LOGICAL,
   PNE_P3_MMX_INSTR_TYPE_EXEC_ARITHMETIC,
   PNE_P3_FP_MMX_TRANS_MMX_TO_FP,
   PNE_P3_FP_MMX_TRANS_FP_TO_MMX,
   PNE_P3_MMX_ASSIST,
   PNE_P3_SEG_RENAME_STALLS_ES,
   PNE_P3_SEG_RENAME_STALLS_DS,
   PNE_P3_SEG_RENAME_STALLS_FS,
   PNE_P3_SEG_RENAME_STALLS_GS,
   PNE_P3_SEG_RENAME_STALLS_TOT,
   PNE_P3_SEG_REG_RENAMES_ES,
   PNE_P3_SEG_REG_RENAMES_DS,
   PNE_P3_SEG_REG_RENAMES_FS,
   PNE_P3_SEG_REG_RENAMES_GS,
   PNE_P3_SEG_REG_RENAMES_TOT,
   PNE_P3_RET_SEG_RENAMES,
   PNE_P3_LAST_NATIVE_EVENT
};
/* These are special Pentium III events with MESI bits set as used in the preset table */
#define PNE_P3_L2_IFETCH_MESI (PNE_P3_L2_IFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P3_L2_LD_MESI     (PNE_P3_L2_LD | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P3_L2_ST_MESI     (PNE_P3_L2_ST | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P3_L2_RQSTS_S     (PNE_P3_L2_RQSTS | MOESI_S)
#define PNE_P3_L2_RQSTS_MESI  (PNE_P3_L2_RQSTS | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)

/* Pentium M enumerations */
enum {
   PNE_PM_DATA_MEM_REFS = 0x40000000,
   PNE_PM_DCU_LINES_IN,
   PNE_PM_DCU_M_LINES_IN,
   PNE_PM_DCU_M_LINES_OUT,
   PNE_PM_DCU_MISS_OUTSTANDING,
   PNE_PM_IFU_IFETCH,
   PNE_PM_IFU_IFETCH_MISS,
   PNE_PM_ITLB_MISS,
   PNE_PM_IFU_MEM_STALL,
   PNE_PM_ILD_STALL,

   PNE_PM_L2_IFETCH,
   PNE_PM_L2_LD,

   PNE_PM_L2_LD_HWD_PREFETCHED,
   PNE_PM_L2_LD_TOT,

   PNE_PM_L2_ST,
   PNE_PM_L2_LINES_IN,

   PNE_PM_L2_HWD_PREFETCHED_LINES_IN,
   PNE_PM_L2_TOT_LINES_IN,

   PNE_PM_L2_MOD_LINES_OUT,

   PNE_PM_L2_HWD_PREFETCHED_LINES_OUT,
   PNE_PM_L2_TOT_LINES_OUT,
   PNE_PM_L2_M_LINES_INM,

   PNE_PM_L2_M_LINES_OUTM,

   PNE_PM_L2_M_LINES_OUTM_HWD_PREFETCHED,
   PNE_PM_L2_M_LINES_OUTM_TOT,

   PNE_PM_L2_RQSTS,

   PNE_PM_L2_ADS,
   PNE_PM_L2_DBS_BUSY,
   PNE_PM_L2_DBS_BUSY_RD,
   PNE_PM_BUS_DRDY_CLOCKS_SELF,
   PNE_PM_BUS_DRDY_CLOCKS_ANY,
   PNE_PM_BUS_LOCK_CLOCKS_SELF,
   PNE_PM_BUS_LOCK_CLOCKS_ANY,
   PNE_PM_BUS_REQ_OUTSTANDING,
   PNE_PM_BUS_TRAN_BRD_SELF,
   PNE_PM_BUS_TRAN_BRD_ANY,
   PNE_PM_BUS_TRAN_RFO_SELF,
   PNE_PM_BUS_TRAN_RFO_ANY,
   PNE_PM_BUS_TRANS_WB_SELF,
   PNE_PM_BUS_TRANS_WB_ANY,
   PNE_PM_BUS_TRAN_IFETCH_SELF,
   PNE_PM_BUS_TRAN_IFETCH_ANY,
   PNE_PM_BUS_TRAN_INVAL_SELF,
   PNE_PM_BUS_TRAN_INVAL_ANY,
   PNE_PM_BUS_TRAN_PWR_SELF,
   PNE_PM_BUS_TRAN_PWR_ANY,
   PNE_PM_BUS_TRANS_P_SELF,
   PNE_PM_BUS_TRANS_P_ANY,
   PNE_PM_BUS_TRANS_IO_SELF,
   PNE_PM_BUS_TRANS_IO_ANY,
   PNE_PM_BUS_TRAN_DEF_SELF,
   PNE_PM_BUS_TRAN_DEF_ANY,
   PNE_PM_BUS_TRAN_BURST_SELF,
   PNE_PM_BUS_TRAN_BURST_ANY,
   PNE_PM_BUS_TRAN_ANY_SELF,
   PNE_PM_BUS_TRAN_ANY_ANY,
   PNE_PM_BUS_TRAN_MEM_SELF,
   PNE_PM_BUS_TRAN_MEM_ANY,
   PNE_PM_BUS_DATA_RCV,
   PNE_PM_BUS_BNR_DRV,
   PNE_PM_BUS_HIT_DRV,
   PNE_PM_BUS_HITM_DRV,
   PNE_PM_BUS_SNOOP_STALL,
   PNE_PM_FLOPS,
   PNE_PM_FP_COMP_OPS_EXE,
   PNE_PM_FP_ASSIST,
   PNE_PM_MUL,
   PNE_PM_DIV,
   PNE_PM_CYCLES_DIV_BUSY,
   PNE_PM_LD_BLOCKS,
   PNE_PM_SB_DRAINS,
   PNE_PM_MISALIGN_MEM_REF,
   PNE_PM_EMON_KNI_PREF_DISPATCHED_PREFETCH_NTA,
   PNE_PM_EMON_KNI_PREF_DISPATCHED_PREFETCH_T1,
   PNE_PM_EMON_KNI_PREF_DISPATCHED_PREFETCH_T2,
   PNE_PM_EMON_KNI_PREF_DISPATCHED_WEAKLY_ORDERED_STORES,
   PNE_PM_EMON_KNI_PREF_MISS_PREFETCH_NTA,
   PNE_PM_EMON_KNI_PREF_MISS_PREFETCH_T1,
   PNE_PM_EMON_KNI_PREF_MISS_PREFETCH_T2,
   PNE_PM_EMON_KNI_PREF_MISS_WEAKLY_ORDERED_STORES,
   PNE_PM_INST_RETIRED,
   PNE_PM_UOPS_RETIRED,
   PNE_PM_INST_DECODED,
   PNE_PM_EMON_SSE_SSE2_INST_RETIRED_PACKED_AND_SCALAR_SINGLE,
   PNE_PM_EMON_SSE_SSE2_INST_RETIRED_SCALAR_SINGLE,
   PNE_PM_EMON_SSE_SSE2_INST_RETIRED_PACKED_DOUBLE,
   PNE_PM_EMON_SSE_SSE2_INST_RETIRED_SCALAR_DOUBLE,
   PNE_PM_EMON_SSE_SSE2_COMP_INST_RETIRED_PACKED_SINGLE,
   PNE_PM_EMON_SSE_SSE2_COMP_INST_RETIRED_SCALAR_SINGLE,
   PNE_PM_EMON_SSE_SSE2_COMP_INST_RETIRED_PACKED_DOUBLE,
   PNE_PM_EMON_SSE_SSE2_COMP_INST_RETIRED_SCALAR_DOUBLE,
   PNE_PM_EMON_EST_TRANS,
   PNE_PM_EMON_EST_TRANS_FREQ,
   PNE_PM_EMON_THERMAL_TRIP,
   PNE_PM_EMON_SIMD_INSTR_RETIRED,
   PNE_PM_EMON_SYNCH_UOPS,
   PNE_PM_EMON_ESP_UOPS,
   PNE_PM_EMON_FUSED_UOPS_RET,
   PNE_PM_EMON_FUSED_UOPS_RET_LD_ONLY,
   PNE_PM_EMON_FUSED_UOPS_RET_STD_ONLY,
   PNE_PM_EMON_UNFUSION,
   PNE_PM_EMON_PREF_RQSTS_UP,
   PNE_PM_EMON_PREF_RQSTS_DN,
   PNE_PM_HW_INT_RX,
   PNE_PM_CYCLES_INT_MASKED,
   PNE_PM_CYCLES_INT_PENDING_AND_MASKED,
   PNE_PM_BR_INST_EXEC,
   PNE_PM_BR_MISSP_EXEC,
   PNE_PM_BR_BAC_MISSP_EXEC,
   PNE_PM_BR_CND_EXEC,
   PNE_PM_BR_CND_MISSP_EXEC,
   PNE_PM_BR_IND_EXEC,
   PNE_PM_BR_IND_MISSP_EXEC,
   PNE_PM_BR_RET_EXEC,
   PNE_PM_BR_RET_MISSP_EXEC,
   PNE_PM_BR_RET_BAC_MISSP_EXEC,
   PNE_PM_BR_CALL_EXEC,
   PNE_PM_BR_CALL_MISSP_EXEC,
   PNE_PM_BR_IND_CALL_EXEC,
   PNE_PM_BR_INST_RETIRED,
   PNE_PM_BR_MISS_PRED_RETIRED,
   PNE_PM_BR_TAKEN_RETIRED,
   PNE_PM_BR_MISS_PRED_TAKEN_RET,
   PNE_PM_BR_INST_DECODED,
   PNE_PM_BTB_MISSES,
   PNE_PM_BR_BOGUS,
   PNE_PM_BACLEARS,
   PNE_PM_RESOURCE_STALLS,
   PNE_PM_PARTIAL_RAT_STALLS,
   PNE_PM_SEGMENT_REG_LOADS,
   PNE_PM_CPU_CLK_UNHALTED,
   PNE_PM_MMX_SAT_INSTR_EXEC,
   PNE_PM_MMX_UOPS_EXEC,
   PNE_PM_MMX_INSTR_TYPE_EXEC_MUL,
   PNE_PM_MMX_INSTR_TYPE_EXEC_SHIFT,
   PNE_PM_MMX_INSTR_TYPE_EXEC_PACK_OPS,
   PNE_PM_MMX_INSTR_TYPE_EXEC_UNPACK_OPS,
   PNE_PM_MMX_INSTR_TYPE_EXEC_LOGICAL,
   PNE_PM_MMX_INSTR_TYPE_EXEC_ARITHMETIC,
   PNE_PM_FP_MMX_TRANS_MMX_TO_FP,
   PNE_PM_FP_MMX_TRANS_FP_TO_MMX,
   PNE_PM_MMX_ASSIST,
   PNE_PM_SEG_RENAME_STALLS_ES,
   PNE_PM_SEG_RENAME_STALLS_DS,
   PNE_PM_SEG_RENAME_STALLS_FS,
   PNE_PM_SEG_RENAME_STALLS_GS,
   PNE_PM_SEG_RENAME_STALLS_TOT,
   PNE_PM_SEG_REG_RENAMES_ES,
   PNE_PM_SEG_REG_RENAMES_DS,
   PNE_PM_SEG_REG_RENAMES_FS,
   PNE_PM_SEG_REG_RENAMES_GS,
   PNE_PM_SEG_REG_RENAMES_TOT,
   PNE_PM_RET_SEG_RENAMES,
   PNE_PM_LAST_NATIVE_EVENT
};
/* These are special Pentium M events with MESI bits set as used in the preset table */
#define PNE_PM_L2_IFETCH_MESI (PNE_PM_L2_IFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_PM_L2_LD_MESI     (PNE_PM_L2_LD | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_PM_L2_ST_MESI     (PNE_PM_L2_ST | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_PM_L2_RQSTS_S     (PNE_PM_L2_RQSTS | MOESI_S)
#define PNE_PM_L2_RQSTS_MESI  (PNE_PM_L2_RQSTS | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)

/* Pentium Core enumerations */
enum {
   PNE_CORE_UNHLTCORE_CYCLES = 0x40000000,
   PNE_CORE_UNHLTREF_CYCLES,
   PNE_CORE_INSTR_RETIRED,
   PNE_CORE_LLC_REFERENCE,
   PNE_CORE_LLC_MISSES,
   PNE_CORE_BR_RETIRED,
   PNE_CORE_MISPREDBR_RETIRED,
   PNE_CORE_LD_BLOCKS,
   PNE_CORE_SD_DRAINS,
   PNE_CORE_MISALIGN_MEM_REF,
   PNE_CORE_SEG_REG_LOADS,
   PNE_CORE_SSE_PREFNTA_RET,
   PNE_CORE_SSE_PREFT1_RET,
   PNE_CORE_SSE_PREFT2_RET,
   PNE_CORE_SSE_NTSTORES_RET,
   PNE_CORE_FP_COMPS_OP_EXE,
// 0x40000010
   PNE_CORE_FP_ASSIST,
   PNE_CORE_MUL,
   PNE_CORE_DIV,
   PNE_CORE_CYCLES_DIV_BUSY,
   PNE_CORE_L2_ADS_SELF,
   PNE_CORE_L2_ADS_BOTH_CORES,
   PNE_CORE_DBUS_BUSY_SELF,
   PNE_CORE_DBUS_BUSY_BOTH_CORES,
   PNE_CORE_DBUS_BUSY_RD_SELF,
   PNE_CORE_DBUS_BUSY_RD_BOTH_CORES,
   PNE_CORE_L2_LINES_IN_SELF_ANY,
   PNE_CORE_L2_LINES_IN_SELF_DEMAND,
   PNE_CORE_L2_LINES_IN_SELF_PREFETCH,
   PNE_CORE_L2_LINES_IN_BOTH_CORES_ANY,
   PNE_CORE_L2_LINES_IN_BOTH_CORES_DEMAND,
   PNE_CORE_L2_LINES_IN_BOTH_CORES_PREFETCH,
// 0x40000020
   PNE_CORE_L2_M_LINES_IN_SELF,
   PNE_CORE_L2_M_LINES_IN_BOTH_CORES,
   PNE_CORE_L2_LINES_OUT_SELF_ANY,
   PNE_CORE_L2_LINES_OUT_SELF_DEMAND,
   PNE_CORE_L2_LINES_OUT_SELF_PREFETCH,
   PNE_CORE_L2_LINES_OUT_BOTH_CORES_ANY,
   PNE_CORE_L2_LINES_OUT_BOTH_CORES_DEMAND,
   PNE_CORE_L2_LINES_OUT_BOTH_CORES_PREFETCH,
   PNE_CORE_L2_M_LINES_OUT_SELF_ANY,
   PNE_CORE_L2_M_LINES_OUT_SELF_DEMAND,
   PNE_CORE_L2_M_LINES_OUT_SELF_PREFETCH,
   PNE_CORE_L2_M_LINES_OUT_BOTH_CORES_ANY,
   PNE_CORE_L2_M_LINES_OUT_BOTH_CORES_DEMAND,
   PNE_CORE_L2_M_LINES_OUT_BOTH_CORES_PREFETCH,
   PNE_CORE_L2_IFETCH_SELF,
   PNE_CORE_L2_IFETCH_BOTH_CORES,
// 0x40000030
   PNE_CORE_L2_LD_SELF_ANY,
   PNE_CORE_L2_LD_SELF_DEMAND,
   PNE_CORE_L2_LD_SELF_PREFETCH,
   PNE_CORE_L2_LD_BOTH_CORES_ANY,
   PNE_CORE_L2_LD_BOTH_CORES_DEMAND,
   PNE_CORE_L2_LD_BOTH_CORES_PREFETCH,
   PNE_CORE_L2_ST_SELF,
   PNE_CORE_L2_ST_BOTH_CORES,
   PNE_CORE_L2_RQSTS_SELF_ANY,
   PNE_CORE_L2_RQSTS_SELF_DEMAND,
   PNE_CORE_L2_RQSTS_SELF_PREFETCH,
   PNE_CORE_L2_RQSTS_BOTH_CORES_ANY,
   PNE_CORE_L2_RQSTS_BOTH_CORES_DEMAND,
   PNE_CORE_L2_RQSTS_BOTH_CORES_PREFETCH,
   PNE_CORE_L2_REJECT_CYCLES_SELF_ANY,
   PNE_CORE_L2_REJECT_CYCLES_SELF_DEMAND,
// 0x40000040
   PNE_CORE_L2_REJECT_CYCLES_SELF_PREFETCH,
   PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_ANY,
   PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_DEMAND,
   PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_PREFETCH,
   PNE_CORE_L2_NO_REQUEST_CYCLES_SELF,
   PNE_CORE_L2_NO_REQUEST_CYCLES_BOTH_CORES,
   PNE_CORE_EST_TRANS_ALL,
   PNE_CORE_EST_TRANS_ALL_FREQUENCY,
   PNE_CORE_THERMAL_TRIP,
   PNE_CORE_NONHLT_REF_CYCLES,
   PNE_CORE_SERIAL_EXECUTION_CYCLES,
   PNE_CORE_DCACHE_CACHE_LD,
   PNE_CORE_DCACHE_CACHE_ST,
   PNE_CORE_DCACHE_CACHE_LOCK,
   PNE_CORE_DATA_MEM_REF,
   PNE_CORE_DATA_MEM_CACHE_REF,
// 0x40000050
   PNE_CORE_DCACHE_REPL,
   PNE_CORE_DCACHE_M_REPL,
   PNE_CORE_DCACHE_M_EVICT,
   PNE_CORE_DCACHE_PEND_MISS,
   PNE_CORE_DTLB_MISS,
   PNE_CORE_SSE_PREFNTA_MISS,
   PNE_CORE_SSE_PREFT1_MISS,
   PNE_CORE_SSE_PREFT2_MISS,
   PNE_CORE_SSE_NTSTORES_MISS,
   PNE_CORE_L1_PREF_REQ,
   PNE_CORE_BUS_REQ_OUTSTANDING_SELF,
   PNE_CORE_BUS_REQ_OUTSTANDING_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_REQ_OUTSTANDING_ALL_AGENTS,
   PNE_CORE_BUS_BNR_CLOCKS,
   PNE_CORE_BUS_DRDY_CLOCKS_THIS_AGENT,
   PNE_CORE_BUS_DRDY_CLOCKS_ALL_AGENTS,
// 0x40000060
   PNE_CORE_BUS_LOCKS_CLOCKS_SELF,
   PNE_CORE_BUS_LOCKS_CLOCKS_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_LOCKS_CLOCKS_ALL_AGENTS,
   PNE_CORE_BUS_DATA_RCV,
   PNE_CORE_BUS_TRANS_BRD_SELF,
   PNE_CORE_BUS_TRANS_BRD_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_BRD_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_RFO_SELF,
   PNE_CORE_BUS_TRANS_RFO_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_RFO_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_IFETCH_SELF,
   PNE_CORE_BUS_TRANS_IFETCH_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_IFETCH_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_INVAL_SELF,
   PNE_CORE_BUS_TRANS_INVAL_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_INVAL_ALL_AGENTS,
// 0x40000070
   PNE_CORE_BUS_TRANS_PWR_SELF,
   PNE_CORE_BUS_TRANS_PWR_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_PWR_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_P_SELF,
   PNE_CORE_BUS_TRANS_P_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_P_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_IO_SELF,
   PNE_CORE_BUS_TRANS_IO_BOTH_CORES_THIS_AGENT,
   PNE_CORE_BUS_TRANS_IO_ALL_AGENTS,
   PNE_CORE_BUS_TRANS_DEF,
   PNE_CORE_BUS_TRANS_WB,
   PNE_CORE_BUS_TRANS_BURST,
   PNE_CORE_BUS_TRANS_MEM,
   PNE_CORE_BUS_TRANS_ANY,
   PNE_CORE_BUS_SNOOPS,
   PNE_CORE_DCU_SNOOP_TO_SHARE,
// 0x40000080
   PNE_CORE_BUS_NOT_IN_USE,
   PNE_CORE_BUS_SNOOP_STALL,
   PNE_CORE_ICACHE_READS,
   PNE_CORE_ICACHE_MISSES,
   PNE_CORE_ITLB_MISSES,
   PNE_CORE_IFU_MEM_STALL,
   PNE_CORE_ILD_STALL,
   PNE_CORE_BR_INST_EXEC,
   PNE_CORE_BR_MISSP_EXEC,
   PNE_CORE_BR_BAC_MISSP_EXEC,
   PNE_CORE_BR_CND_EXEC,
   PNE_CORE_BR_CND_MISSP_EXEC,
   PNE_CORE_BR_IND_EXEC,
   PNE_CORE_BR_IND_MISSP_EXEC,
   PNE_CORE_BR_RET_EXEC,
   PNE_CORE_BR_RET_MISSP_EXEC,
// 0x40000090
   PNE_CORE_BR_RET_BAC_MISSP_EXEC,
   PNE_CORE_BR_CALL_EXEC,
   PNE_CORE_BR_CALL_MISSP_EXEC,
   PNE_CORE_BR_IND_CALL_EXEC,
   PNE_CORE_RESOURCE_STALL,
   PNE_CORE_MMX_INSTR_EXEC,
   PNE_CORE_SIMD_INT_SAT_EXEC,
   PNE_CORE_SIMD_INT_PMUL_EXEC,
   PNE_CORE_SIMD_INT_PSFT_EXEC,
   PNE_CORE_SIMD_INT_PCK_EXEC,
   PNE_CORE_SIMD_INT_UPCK_EXEC,
   PNE_CORE_SIMD_INT_PLOG_EXEC,
   PNE_CORE_SIMD_INT_PARI_EXEC,
   PNE_CORE_INSTR_RET,
   PNE_CORE_FP_COMP_INSTR_RET,
   PNE_CORE_UOPS_RET,
// 0x400000A0
   PNE_CORE_SMC_DETECTED,
   PNE_CORE_BR_INSTR_RET,
   PNE_CORE_BR_MISPRED_RET,
   PNE_CORE_CYCLES_INT_MASKED,
   PNE_CORE_CYCLES_INT_PEDNING_MASKED,
   PNE_CORE_HW_INT_RX,
   PNE_CORE_BR_TAKEN_RET,
   PNE_CORE_BR_MISPRED_TAKEN_RET,
   PNE_CORE_MMX_FP_TRANS,
   PNE_CORE_FP_MMX_TRANS,
   PNE_CORE_MMX_ASSIST,
   PNE_CORE_MMX_INSTR_RET,
   PNE_CORE_INSTR_DECODED,
   PNE_CORE_ESP_UOPS,
   PNE_CORE_SIMD_FP_SP_RET,
   PNE_CORE_SIMD_FP_SP_S_RET,
// 0x400000B0
   PNE_CORE_SIMD_FP_DP_P_RET,
   PNE_CORE_SIMD_FP_DP_S_RET,
   PNE_CORE_SIMD_INT_128_RET,
   PNE_CORE_SIMD_FP_SP_P_COMP_RET,
   PNE_CORE_SIMD_FP_SP_S_COMP_RET,
   PNE_CORE_SIMD_FP_DP_P_COMP_RET,
   PNE_CORE_SIMD_FP_DP_S_COMP_RET,
   PNE_CORE_FUSED_UOPS_RET,
   PNE_CORE_FUSED_LD_UOPS_RET,
   PNE_CORE_FUSED_ST_UOPS_RET,
   PNE_CORE_UNFUSION,
   PNE_CORE_BR_INSTR_DECODED,
   PNE_CORE_BTB_MISSES,
   PNE_CORE_BR_BOGUS,
   PNE_CORE_BACLEARS,
   PNE_CORE_PREF_RQSTS_UP,
// 0x400000C0
   PNE_CORE_PREF_RQSTS_DN,
   PNE_CORE_LAST_NATIVE_EVENT /* used to initialize sub_info.num_native_events */
};

/* These are special Pentium M events with MESI bits set as used in the preset table */
#define PNE_CORE_L2_IFETCH_SELF_MESI (PNE_CORE_L2_IFETCH_SELF | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_IFETCH_BOTH_CORES_MESI (PNE_CORE_L2_IFETCH_BOTH_CORES | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_SELF_ANY_MESI     (PNE_CORE_L2_LD_SELF_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_SELF_DEMAND_MESI     (PNE_CORE_L2_LD_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_SELF_PREFETCH_MESI     (PNE_CORE_L2_LD_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_BOTH_CORES_ANY_MESI     (PNE_CORE_L2_LD_BOTH_CORES_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_BOTH_CORES_DEMAND_MESI     (PNE_CORE_L2_LD_BOTH_CORES_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_LD_BOTH_CORES_PREFETCH_MESI     (PNE_CORE_L2_LD_BOTH_CORES_PREFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_ST_SELF_MESI     (PNE_CORE_L2_ST_SELF | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_ST_BOTH_CORES_MESI     (PNE_CORE_L2_ST_BOTH_CORES | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_SELF_ANY_MESI     (PNE_CORE_L2_RQSTS_SELF_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_SELF_ANY_S     (PNE_CORE_L2_RQSTS_SELF_ANY | MOESI_S)
#define PNE_CORE_L2_RQSTS_SELF_DEMAND_MESI     (PNE_CORE_L2_RQSTS_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_SELF_PREFETCH_MESI     (PNE_CORE_L2_RQSTS_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_BOTH_CORES_ANY_MESI     (PNE_CORE_L2_RQSTS_BOTH_CORES_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_BOTH_CORES_DEMAND_MESI     (PNE_CORE_L2_RQSTS_BOTH_CORES_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_RQSTS_BOTH_CORES_PREFETCH_MESI     (PNE_CORE_L2_RQSTS_BOTH_CORES_PREFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_SELF_ANY_MESI     (PNE_CORE_L2_REJECT_CYCLES_SELF_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_SELF_DEMAND_MESI     (PNE_CORE_L2_REJECT_CYCLES_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_SELF_PREFETCH_MESI     (PNE_CORE_L2_REJECT_CYCLES_SELF_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_ANY_MESI     (PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_ANY | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_DEMAND_MESI     (PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_DEMAND | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_PREFETCH_MESI     (PNE_CORE_L2_REJECT_CYCLES_BOTH_CORES_PREFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)

/* Pentium II enumerations */
enum {
   PNE_P2_DATA_MEM_REFS = 0x40000000,
   PNE_P2_DCU_LINES_IN,
   PNE_P2_DCU_M_LINES_IN,
   PNE_P2_DCU_M_LINES_OUT,
   PNE_P2_DCU_MISS_OUTSTANDING,
   PNE_P2_IFU_IFETCH,
   PNE_P2_IFU_IFETCH_MISS,
   PNE_P2_ITLB_MISS,
   PNE_P2_IFU_MEM_STALL,
   PNE_P2_ILD_STALL,

   PNE_P2_L2_IFETCH,
   PNE_P2_L2_LD,
   PNE_P2_L2_ST,
   PNE_P2_L2_RQSTS,

   PNE_P2_L2_LINES_IN,
   PNE_P2_L2_LINES_OUT,
   PNE_P2_L2_M_LINES_INM,
   PNE_P2_L2_M_LINES_OUTM,
   PNE_P2_L2_ADS,
   PNE_P2_L2_DBS_BUSY,
   PNE_P2_L2_DBS_BUSY_RD,
   PNE_P2_BUS_DRDY_CLOCKS_SELF,
   PNE_P2_BUS_DRDY_CLOCKS_ANY,
   PNE_P2_BUS_LOCK_CLOCKS_SELF,
   PNE_P2_BUS_LOCK_CLOCKS_ANY,
   PNE_P2_BUS_REQ_OUTSTANDING,
   PNE_P2_BUS_TRAN_BRD_SELF,
   PNE_P2_BUS_TRAN_BRD_ANY,
   PNE_P2_BUS_TRAN_RFO_SELF,
   PNE_P2_BUS_TRAN_RFO_ANY,
   PNE_P2_BUS_TRANS_WB_SELF,
   PNE_P2_BUS_TRANS_WB_ANY,
   PNE_P2_BUS_TRAN_IFETCH_SELF,
   PNE_P2_BUS_TRAN_IFETCH_ANY,
   PNE_P2_BUS_TRAN_INVAL_SELF,
   PNE_P2_BUS_TRAN_INVAL_ANY,
   PNE_P2_BUS_TRAN_PWR_SELF,
   PNE_P2_BUS_TRAN_PWR_ANY,
   PNE_P2_BUS_TRANS_P_SELF,
   PNE_P2_BUS_TRANS_P_ANY,
   PNE_P2_BUS_TRANS_IO_SELF,
   PNE_P2_BUS_TRANS_IO_ANY,
   PNE_P2_BUS_TRAN_DEF_SELF,
   PNE_P2_BUS_TRAN_DEF_ANY,
   PNE_P2_BUS_TRAN_BURST_SELF,
   PNE_P2_BUS_TRAN_BURST_ANY,
   PNE_P2_BUS_TRAN_ANY_SELF,
   PNE_P2_BUS_TRAN_ANY_ANY,
   PNE_P2_BUS_TRAN_MEM_SELF,
   PNE_P2_BUS_TRAN_MEM_ANY,
   PNE_P2_BUS_TRAN_RCV,
   PNE_P2_BUS_BNR_DRV,
   PNE_P2_BUS_HIT_DRV,
   PNE_P2_BUS_HITM_DRV,
   PNE_P2_BUS_SNOOP_STALL,
   PNE_P2_FLOPS,
   PNE_P2_FP_COMP_OPS_EXE,
   PNE_P2_FP_ASSIST,
   PNE_P2_MUL,
   PNE_P2_DIV,
   PNE_P2_CYCLES_DIV_BUSY,
   PNE_P2_LD_BLOCKS,
   PNE_P2_SB_DRAINS,
   PNE_P2_MISALIGN_MEM_REF,
   PNE_P2_INST_RETIRED,
   PNE_P2_UOPS_RETIRED,
   PNE_P2_INST_DECODED,
   PNE_P2_HW_INT_RX,
   PNE_P2_CYCLES_INT_MASKED,
   PNE_P2_CYCLES_INT_PENDING_AND_MASKED,
   PNE_P2_BR_INST_RETIRED,
   PNE_P2_BR_MISS_PRED_RETIRED,
   PNE_P2_BR_TAKEN_RETIRED,
   PNE_P2_BR_MISS_PRED_TAKEN_RET,
   PNE_P2_BR_INST_DECODED,
   PNE_P2_BTB_MISSES,
   PNE_P2_BR_BOGUS,
   PNE_P2_BACLEARS,
   PNE_P2_RESOURCE_STALLS,
   PNE_P2_PARTIAL_RAT_STALLS,
   PNE_P2_SEGMENT_REG_LOADS,
   PNE_P2_CPU_CLK_UNHALTED,
   PNE_P2_MMX_INSTR_EXEC,
   PNE_P2_MMX_SAT_INSTR_EXEC,
   PNE_P2_MMX_UOPS_EXEC,
   PNE_P2_MMX_INSTR_TYPE_EXEC_MUL,
   PNE_P2_MMX_INSTR_TYPE_EXEC_SHIFT,
   PNE_P2_MMX_INSTR_TYPE_EXEC_PACK_OPS,
   PNE_P2_MMX_INSTR_TYPE_EXEC_UNPACK_OPS,
   PNE_P2_MMX_INSTR_TYPE_EXEC_LOGICAL,
   PNE_P2_MMX_INSTR_TYPE_EXEC_ARITHMETIC,
   PNE_P2_FP_MMX_TRANS_MMX_TO_FP,
   PNE_P2_FP_MMX_TRANS_FP_TO_MMX,
   PNE_P2_MMX_ASSIST,
   PNE_P2_MMX_INSTR_RET,
   PNE_P2_SEG_REG_RENAMES_ES,
   PNE_P2_SEG_REG_RENAMES_DS,
   PNE_P2_SEG_REG_RENAMES_FS,
   PNE_P2_SEG_REG_RENAMES_GS,
   PNE_P2_SEG_REG_RENAMES_TOT,
   PNE_P2_RET_SEG_RENAMES,
   PNE_P2_LAST_NATIVE_EVENT
};
/* These are special Pentium II events with MESI bits set as used in the preset table */
#define PNE_P2_L2_IFETCH_MESI (PNE_P2_L2_IFETCH | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P2_L2_LD_MESI     (PNE_P2_L2_LD | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P2_L2_ST_MESI     (PNE_P2_L2_ST | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)
#define PNE_P2_L2_RQSTS_S     (PNE_P2_L2_RQSTS | MOESI_S)
#define PNE_P2_L2_RQSTS_MESI  (PNE_P2_L2_RQSTS | MOESI_M_INTEL | MOESI_E | MOESI_S | MOESI_I)

/* Athlon enumerations */
enum {
   PNE_ATH_SEG_REG_LOADS = 0x40000000,
   PNE_ATH_ST_ACTIVE_IS,
   PNE_ATH_DC_ACCESSES,
   PNE_ATH_DC_MISSES,

   PNE_ATH_L2_DC_REFILLS,
   PNE_ATH_SYS_DC_REFILLS,
   PNE_ATH_DC_WB,

   PNE_ATH_L1_DTLB_MISSES_AND_L2_DTLB_HITS,
   PNE_ATH_L1_AND_L2_DTLB_MISSES,
   PNE_ATH_MISALIGNED_DATA_REFERENCES,
   PNE_ATH_DRAM_SYS_REQS,
   PNE_ATH_SYS_REQS_SEL_TYPE,
   PNE_ATH_SNOOP_HITS,
   PNE_ATH_ECC_ERR,
   PNE_ATH_INTERNAL_CACHE_INV,
   PNE_ATH_TOT_CYC,
   PNE_ATH_L2_REQ,
   PNE_ATH_FILL_REQ_STALLS,
   PNE_ATH_IC_FETCHES,
   PNE_ATH_IC_MISSES,
   PNE_ATH_L2_IC_REFILLS,
   PNE_ATH_SYS_IC_REFILLS,
   PNE_ATH_L1_ITLB_MISSES,
   PNE_ATH_L2_ITLB_MISSES,
   PNE_ATH_SNOOP_RESYNCS,
   PNE_ATH_IFETCH_STALLS,
   PNE_ATH_RET_STACK_HITS,
   PNE_ATH_RET_STACK_OVERFLOW,
   PNE_ATH_RET_INSTRUCTIONS,
   PNE_ATH_RET_OPS,
   PNE_ATH_RET_BR,
   PNE_ATH_RET_BR_MIS,
   PNE_ATH_RET_TAKEN_BR,
   PNE_ATH_RET_TAKEN_BR_MIS,
   PNE_ATH_RET_FAR_CONTROL_TRANSFERS,
   PNE_ATH_RET_RESYNC_BR,
   PNE_ATH_RET_NEAR_RETURNS,
   PNE_ATH_RET_NEAR_RETURNS_MIS,
   PNE_ATH_RET_INDIRECT_BR_MIS,
   PNE_ATH_INTS_MASKED_CYC,
   PNE_ATH_INTS_MASKED_WHILE_PENDING_CYC,
   PNE_ATH_TAKEN_HARDWARE_INTS,
   PNE_ATH_INS_DECODER_EMPTY,
   PNE_ATH_DISPATCH_STALLS,
   PNE_ATH_BRANCH_ABORTS,
   PNE_ATH_SERIALIZE,
   PNE_ATH_SEG_LOAD_STALLS,
   PNE_ATH_ICU_FULL,
   PNE_ATH_RES_STATIONS_FULL,
   PNE_ATH_FPU_FULL,
   PNE_ATH_LS_FULL,
   PNE_ATH_ALL_QUIET_STALL,
   PNE_ATH_TRANS_OR_BRANCH_PENDING,
   PNE_ATH_BP_DR0,
   PNE_ATH_BP_DR1,
   PNE_ATH_BP_DR2,
   PNE_ATH_BP_DR3,
   PNE_ATH_LAST_NATIVE_EVENT
};
/* These are special Athlon events with MOESI bits set as used in the preset table */
#define PNE_ATH_L2_DC_REFILLS_M     (PNE_ATH_L2_DC_REFILLS  | MOESI_M)
#define PNE_ATH_L2_DC_REFILLS_MI    (PNE_ATH_L2_DC_REFILLS  | MOESI_M | MOESI_I)
#define PNE_ATH_L2_DC_REFILLS_OES   (PNE_ATH_L2_DC_REFILLS  | MOESI_O | MOESI_E | MOESI_S)
#define PNE_ATH_L2_DC_REFILLS_MOES  (PNE_ATH_L2_DC_REFILLS  | MOESI_M | MOESI_O | MOESI_E | MOESI_S)
#define PNE_ATH_SYS_DC_REFILLS_M    (PNE_ATH_SYS_DC_REFILLS | MOESI_M)
#define PNE_ATH_SYS_DC_REFILLS_MOES (PNE_ATH_SYS_DC_REFILLS | MOESI_M | MOESI_O | MOESI_E | MOESI_S)
#define PNE_ATH_SYS_DC_REFILLS_OES  (PNE_ATH_SYS_DC_REFILLS | MOESI_O | MOESI_E | MOESI_S)

/* Opteron enumerations */
enum {
   PNE_OPT_FP_ADD_PIPE = 0x40000000,
   PNE_OPT_FP_MULT_PIPE,
   PNE_OPT_FP_MULT_AND_ADD_PIPE,
   PNE_OPT_FP_ST_PIPE,
   PNE_OPT_FP_ADD_PIPE_LOAD,
   PNE_OPT_FP_MULT_PIPE_LOAD,
   PNE_OPT_FP_ST_PIPE_LOAD,
   PNE_OPT_FP_ST_PIPE_AND_LOAD,
   PNE_OPT_FP_NONE_RET,
   PNE_OPT_FP_FAST_FLAG,
   PNE_OPT_LS_SEG_REG_LOADS_ES,
   PNE_OPT_LS_SEG_REG_LOADS_CS,
   PNE_OPT_LS_SEG_REG_LOADS_SS,
   PNE_OPT_LS_SEG_REG_LOADS_DS,
   PNE_OPT_LS_SEG_REG_LOADS_FS,
   PNE_OPT_LS_SEG_REG_LOADS_GS,
   PNE_OPT_LS_SEG_REG_LOADS_HS,
   PNE_OPT_LS_SELF_MODIFYING_RESYNC,
   PNE_OPT_LS_SNOOP_RESYNC,
   PNE_OPT_LS_BUF_2_FULL,
   PNE_OPT_LS_LOCK_INS,
   PNE_OPT_LS_LOCK_REQ,
   PNE_OPT_LS_LOCK_COMP,
   PNE_OPT_LS_LATE_CANCEL,
   PNE_OPT_LS_CFLUSH,
   PNE_OPT_LS_CPUID,
   PNE_OPT_MEM_RQ_UC,
   PNE_OPT_MEM_RQ_WC,
   PNE_OPT_MEM_RQ_SS,
   PNE_OPT_DC_ACCESS,
   PNE_OPT_DC_MISS,
   PNE_OPT_DC_L2_REFILL,
   PNE_OPT_DC_SYS_REFILL,
   PNE_OPT_DC_COPYBACK,
   PNE_OPT_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT,
   PNE_OPT_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,
   PNE_OPT_DC_MISALIGNED_DATA_REF,
   PNE_OPT_DC_LATE_CANCEL,
   PNE_OPT_DC_EARLY_CANCEL,
   PNE_OPT_DC_ECC_SCRUBBER_ERR,
   PNE_OPT_DC_ECC_PIGGY_SCRUBBER_ERR,
   PNE_OPT_DC_DISPATCHED_PREFETCH_LOAD,
   PNE_OPT_DC_DISPATCHED_PREFETCH_STORE,
   PNE_OPT_DC_DISPATCHED_PREFETCH_NTA,
   PNE_OPT_DC_ACCESSES_BY_LOCK,
   PNE_OPT_DC_MISSES_BY_LOCK,
   PNE_OPT_SI_PREFETCH_CANCEL,
   PNE_OPT_SI_PREFETCH_ATTEMPT,
   PNE_OPT_SI_RD_RESP_EXCL,
   PNE_OPT_SI_RD_RESP_MOD,
   PNE_OPT_SI_RD_RESP_SHR,
   PNE_OPT_BU_L2_REQ_IC,
   PNE_OPT_BU_L2_REQ_DC,
   PNE_OPT_BU_L2_REQ_TLB_RELOAD,
   PNE_OPT_BU_L2_REQ_TAG_SNOOP_REQ,
   PNE_OPT_BU_L2_REQ_CANC_REQ,
   PNE_OPT_BU_L2_FILL_MISS_IC,
   PNE_OPT_BU_L2_FILL_MISS_DC,
   PNE_OPT_BU_L2_FILL_MISS_TLB_RELOAD,
   PNE_OPT_BU_L2_FILL_DIRTY,
   PNE_OPT_BU_L2_FILL_FROM_L1,
   PNE_OPT_IC_FETCH,
   PNE_OPT_IC_MISS,
   PNE_OPT_IC_L2_REFILL,
   PNE_OPT_IC_SYS_REFILL,
   PNE_OPT_IC_L1ITLB_MISS_AND_L2ITLB_HIT,
   PNE_OPT_IC_L1ITLB_MISS_AND_L2ITLB_MISS,
   PNE_OPT_IC_RESYNC,
   PNE_OPT_IC_FETCH_STALL,
   PNE_OPT_IC_STACK_HIT,
   PNE_OPT_IC_STACK_OVERFLOW,
   PNE_OPT_FR_X86_INS,
   PNE_OPT_FR_RET_UOPS,
   PNE_OPT_FR_BR,
   PNE_OPT_FR_BR_MIS,
   PNE_OPT_FR_BR_TAKEN,
   PNE_OPT_FR_BR_TAKEN_MIS,
   PNE_OPT_FR_FAR_CONTROL_TRANSFERS,
   PNE_OPT_FR_RESYNCS,
   PNE_OPT_FR_NEAR_RETURNS,
   PNE_OPT_FR_NEAR_RETURNS_MIS,
   PNE_OPT_FR_BR_MISCOMPARE,
   PNE_OPT_FR_FPU_X87,
   PNE_OPT_FR_FPU_MMX_3D,
   PNE_OPT_FR_FPU_SSE_SSE2_PACKED,
   PNE_OPT_FR_FPU_SSE_SSE2_SCALAR,
   PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR,
   PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED,
   PNE_OPT_FR_FASTPATH_POS0,
   PNE_OPT_FR_FASTPATH_POS1,
   PNE_OPT_FR_FASTPATH_POS2,
   PNE_OPT_FR_INTS_MASKED,
   PNE_OPT_FR_INTS_MASKED_PENDING,
   PNE_OPT_FR_HW_INTS,
   PNE_OPT_FR_DECODER_EMPTY,
   PNE_OPT_FR_DISPATCH_STALLS,
   PNE_OPT_FR_DISPATCH_STALLS_BR,
   PNE_OPT_FR_DISPATCH_STALLS_SER,
   PNE_OPT_FR_DISPATCH_STALLS_SEG,
   PNE_OPT_FR_DISPATCH_STALLS_FULL_REORDER,
   PNE_OPT_FR_DISPATCH_STALLS_FULL_RESERVATION,
   PNE_OPT_FR_DISPATCH_STALLS_FULL_FPU,
   PNE_OPT_FR_DISPATCH_STALLS_FULL_LS,
   PNE_OPT_FR_DISPATCH_STALLS_QUIET,
   PNE_OPT_FR_DISPATCH_STALLS_FAR,
   PNE_OPT_FR_FPU_EXCEPTIONS_X87,
   PNE_OPT_FR_FPU_EXCEPTIONS_SSE_RETYPE,
   PNE_OPT_FR_FPU_EXCEPTIONS_SSE_RECLASS,
   PNE_OPT_FR_FPU_EXCEPTIONS_SSE_MICROTRAPS,
   PNE_OPT_FR_BP_DR0,
   PNE_OPT_FR_BP_DR1,
   PNE_OPT_FR_BP_DR2,
   PNE_OPT_FR_BP_DR3,
   PNE_OPT_NB_MC_PAGE_HIT,
   PNE_OPT_NB_MC_PAGE_MISS,
   PNE_OPT_NB_MC_PAGE_CONFLICT,
   PNE_OPT_NB_MC_PAGE_TBL_OVERFLOW,
   PNE_OPT_NB_MC_DRAM,
   PNE_OPT_NB_MC_TURNAROUND_DIMM,
   PNE_OPT_NB_MC_TURNAROUND_RTW,
   PNE_OPT_NB_MC_TURNAROUND_WTR,
   PNE_OPT_NB_MC_BYPASS_HP,
   PNE_OPT_NB_MC_BYPASS_LP,
   PNE_OPT_NB_MC_BYPASS_INTERFACE,
   PNE_OPT_NB_MC_BYPASS_QUEUE,
   PNE_OPT_NB_SIZED_NONPOSTWRSZBYTE,
   PNE_OPT_NB_SIZED_NONPOSTWRSZDWORD,
   PNE_OPT_NB_SIZED_POSTWRSZBYTE,
   PNE_OPT_NB_SIZED_POSTWRSZDWORD,
   PNE_OPT_NB_SIZED_RDSZBYTE,
   PNE_OPT_NB_SIZED_RDSZDWORD,
   PNE_OPT_NB_SIZED_RDMODWR,
   PNE_OPT_NB_PROBE_MISS,
   PNE_OPT_NB_PROBE_HIT,
   PNE_OPT_NB_PROBE_HIT_DIRTY_NO_MEM_CANCEL,
   PNE_OPT_NB_PROBE_HIT_DIRTY_MEM_CANCEL,
   PNE_OPT_NB_HT_BUS0_COMMAND,
   PNE_OPT_NB_HT_BUS0_DATA,
   PNE_OPT_NB_HT_BUS0_BUFF,
   PNE_OPT_NB_HT_BUS0_NOP,
   PNE_OPT_NB_HT_BUS1_COMMAND,
   PNE_OPT_NB_HT_BUS1_DATA,
   PNE_OPT_NB_HT_BUS1_BUFF,
   PNE_OPT_NB_HT_BUS1_NOP,
   PNE_OPT_NB_HT_BUS2_COMMAND,
   PNE_OPT_NB_HT_BUS2_DATA,
   PNE_OPT_NB_HT_BUS2_BUFF,
   PNE_OPT_NB_HT_BUS2_NOP,
   PNE_OPT_CPU_CLK_UNHALTED,
   PNE_OPT_HT_LL_MEM_XFR,
   PNE_OPT_HT_LR_MEM_XFR,
   PNE_OPT_HT_RL_MEM_XFR,
   PNE_OPT_HT_LL_IO_XFR,
   PNE_OPT_HT_LR_IO_XFR,
   PNE_OPT_HT_RL_IO_XFR,
   PNE_OPT_LAST_NATIVE_EVENT
};
/* These are special Opteron events with MOESI bits set as used in the preset table */
#define PNE_OPT_DC_L2_REFILL_M      (PNE_OPT_DC_L2_REFILL | MOESI_M)
#define PNE_OPT_DC_L2_REFILL_MI     (PNE_OPT_DC_L2_REFILL | MOESI_M | MOESI_I)
#define PNE_OPT_DC_L2_REFILL_OES    (PNE_OPT_DC_L2_REFILL | MOESI_O | MOESI_E | MOESI_S)
#define PNE_OPT_DC_L2_REFILL_OESI   (PNE_OPT_DC_L2_REFILL | MOESI_O | MOESI_E | MOESI_S | MOESI_I)
#define PNE_OPT_DC_L2_REFILL_MOES   (PNE_OPT_DC_L2_REFILL | MOESI_M | MOESI_O | MOESI_E | MOESI_S)
#define PNE_OPT_DC_L2_REFILL_MOESI  (PNE_OPT_DC_L2_REFILL | MOESI_ALL)
#define PNE_OPT_DC_SYS_REFILL_M     (PNE_OPT_DC_SYS_REFILL | MOESI_M)
#define PNE_OPT_DC_SYS_REFILL_OES  (PNE_OPT_DC_SYS_REFILL | MOESI_O | MOESI_E | MOESI_S)
#define PNE_OPT_DC_SYS_REFILL_OESI  (PNE_OPT_DC_SYS_REFILL | MOESI_O | MOESI_E | MOESI_S | MOESI_I)
#define PNE_OPT_DC_SYS_REFILL_MOES  (PNE_OPT_DC_SYS_REFILL | MOESI_M | MOESI_O | MOESI_E | MOESI_S)
#define PNE_OPT_DC_SYS_REFILL_MOESI (PNE_OPT_DC_SYS_REFILL | MOESI_ALL)

/* PAPI preset events are defined in the tables below.
   Each entry consists of a PAPI name, derived info, and up to four
   native event indeces as defined above.
   Events that require tagging should be ordered such that the
   first event is the one that is read. See PAPI_FP_INS for an example.
*/
const hwi_search_t _papi_hwd_p3_preset_map[] = {
   {PAPI_L1_DCM,{0,{PNE_P3_DCU_LINES_IN,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_ICM,{0,{PNE_P3_L2_IFETCH_MESI,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_DCM,{DERIVED_SUB,{PNE_P3_L2_LINES_IN,PNE_P3_BUS_TRAN_IFETCH_SELF,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_ICM, {0, {PNE_P3_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {0, {PNE_P3_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCM, {0, {PNE_P3_L2_LINES_IN, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_SHR, {0, {PNE_P3_L2_RQSTS_S, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_CLN, {0, {PNE_P3_BUS_TRAN_RFO_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_CA_INV, {0, {PNE_P3_BUS_HITM_DRV,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},   */
   {PAPI_CA_ITV, {0, {PNE_P3_BUS_TRAN_INVAL_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_P3_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_P3_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_STM, {0, {PNE_P3_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_LDM, {DERIVED_SUB, {PNE_P3_L2_LINES_IN, PNE_P3_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_STM, {0, {PNE_P3_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BTAC_M, {0, {PNE_P3_BTB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_P3_HW_INT_RX, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_CN, {0, {PNE_P3_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_P3_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_NTK,
    {DERIVED_SUB, {PNE_P3_BR_INST_RETIRED, PNE_P3_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_P3_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_PRC,
    {DERIVED_SUB, {PNE_P3_BR_INST_RETIRED, PNE_P3_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_P3_INST_DECODED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_P3_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_P3_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_OPS, {0, {PNE_P3_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/* Katmai introduced the KNI (Katmai New Instruction) set, including single precision SSE.
   It would be good to support these, but they only matter for SP optimized code, like ATLAS.
   A multiple table approach, like on Pentium 4 would be useful, but requires restructuring.
   Maybe for 4.0...
   {PAPI_FP_OPS, {0, {PNE_P3_FLOPS, PNE_P3_EMON_KNI_COMP_INST_RET_PACKED_AND_SCALAR, PAPI_NULL, PAPI_NULL}, {0,}}},
*/
   {PAPI_BR_INS, {0, {PNE_P3_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_VEC_INS,       {0, {PNE_P3_MMX_INSTR_EXEC,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},  Says event exists on P2 only  */
   {PAPI_RES_STL, {0, {PNE_P3_RESOURCE_STALLS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_P3_CPU_CLK_UNHALTED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH, {DERIVED_SUB, {PNE_P3_DATA_MEM_REFS, PNE_P3_DCU_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_P3_DATA_MEM_REFS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_P3_L2_LD_MESI, PNE_P3_L2_ST_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_P3_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCW, {0, {PNE_P3_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICH, {DERIVED_SUB, {PNE_P3_IFU_IFETCH, PNE_P3_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICH,
    {DERIVED_SUB, {PNE_P3_L2_IFETCH_MESI, PNE_P3_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_P3_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {0, {PNE_P3_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_P3_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICR, {0, {PNE_P3_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCH, {DERIVED_SUB, {PNE_P3_L2_RQSTS_MESI, PNE_P3_L2_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_P3_DATA_MEM_REFS, PNE_P3_IFU_IFETCH, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCA, {0, {PNE_P3_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCR, {DERIVED_ADD, {PNE_P3_L2_LD_MESI, PNE_P3_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCW, {0, {PNE_P3_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FML_INS, {0, {PNE_P3_MUL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FDV_INS, {0, {PNE_P3_DIV, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

const hwi_search_t _papi_hwd_pm_preset_map[] = {
   {PAPI_L1_DCM,{0,{PNE_PM_DCU_LINES_IN,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_ICM,{0,{PNE_PM_L2_IFETCH_MESI,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_DCM,{DERIVED_SUB,{PNE_PM_L2_TOT_LINES_IN,PNE_PM_BUS_TRAN_IFETCH_SELF,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_ICM, {0, {PNE_PM_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {0, {PNE_PM_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCM, {0, {PNE_PM_L2_TOT_LINES_IN, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_SHR, {0, {PNE_PM_L2_RQSTS_S, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_CLN, {0, {PNE_PM_BUS_TRAN_RFO_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_CA_INV, {0, {PNE_PM_BUS_HITM_DRV,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},   */
   {PAPI_CA_ITV, {0, {PNE_PM_BUS_TRAN_INVAL_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_PM_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_PM_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_STM, {0, {PNE_PM_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_LDM, {DERIVED_SUB, {PNE_PM_L2_TOT_LINES_IN, PNE_PM_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_STM, {0, {PNE_PM_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BTAC_M, {0, {PNE_PM_BTB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_PM_HW_INT_RX, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_CN, {0, {PNE_PM_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_PM_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_NTK,
    {DERIVED_SUB, {PNE_PM_BR_INST_RETIRED, PNE_PM_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_PM_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_PRC,
    {DERIVED_SUB, {PNE_PM_BR_INST_RETIRED, PNE_PM_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_PM_INST_DECODED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_PM_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_PM_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_OPS, {0, {PNE_PM_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_PM_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_VEC_INS,       {0, {PNE_PM_MMX_INSTR_EXEC,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},  Says event exists on P2 only  */
   {PAPI_RES_STL, {0, {PNE_PM_RESOURCE_STALLS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_PM_CPU_CLK_UNHALTED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH, {DERIVED_SUB, {PNE_PM_DATA_MEM_REFS, PNE_PM_DCU_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_PM_DATA_MEM_REFS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_PM_L2_LD_MESI, PNE_PM_L2_ST_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_PM_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCW, {0, {PNE_PM_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICH, {DERIVED_SUB, {PNE_PM_IFU_IFETCH, PNE_PM_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICH,
    {DERIVED_SUB, {PNE_PM_L2_IFETCH_MESI, PNE_PM_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_PM_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {0, {PNE_PM_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_PM_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICR, {0, {PNE_PM_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCH, {DERIVED_SUB, {PNE_PM_L2_RQSTS_MESI, PNE_PM_L2_TOT_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_PM_DATA_MEM_REFS, PNE_PM_IFU_IFETCH, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCA, {0, {PNE_PM_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCR, {DERIVED_ADD, {PNE_PM_L2_LD_MESI, PNE_PM_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCW, {0, {PNE_PM_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FML_INS, {0, {PNE_PM_MUL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FDV_INS, {0, {PNE_PM_DIV, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

const hwi_search_t _papi_hwd_core_preset_map[] = {
   {PAPI_L1_DCM,{0,{PNE_CORE_DCACHE_REPL,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_ICM,{0,{PNE_CORE_L2_IFETCH_SELF_MESI,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_DCM,{DERIVED_SUB,{PNE_CORE_L2_LINES_IN_SELF_ANY,PNE_CORE_BUS_TRANS_IFETCH_SELF,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_ICM, {0, {PNE_CORE_BUS_TRANS_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {0, {PNE_CORE_L2_RQSTS_SELF_DEMAND_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCM, {0, {PNE_CORE_L2_LINES_IN_SELF_ANY, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_SHR, {0, {PNE_CORE_L2_RQSTS_SELF_ANY_S, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_CLN, {0, {PNE_CORE_BUS_TRANS_RFO_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_CA_INV, {0, {PNE_PM_BUS_HITM_DRV,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},   */
   {PAPI_CA_ITV, {0, {PNE_CORE_BUS_TRANS_INVAL_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_CORE_ITLB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_CORE_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_CORE_L2_LD_SELF_ANY_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_STM, {0, {PNE_CORE_L2_ST_SELF_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_LDM, {DERIVED_SUB, {PNE_CORE_L2_LINES_IN_SELF_ANY, PNE_CORE_L2_M_LINES_IN_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_STM, {0, {PNE_CORE_L2_M_LINES_IN_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BTAC_M, {0, {PNE_CORE_BTB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_CORE_HW_INT_RX, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_CN, {0, {PNE_CORE_BR_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_CORE_BR_TAKEN_RET, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_NTK,
    {DERIVED_SUB, {PNE_CORE_BR_RETIRED, PNE_CORE_BR_TAKEN_RET, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_CORE_MISPREDBR_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_PRC,
    {DERIVED_SUB, {PNE_CORE_BR_RETIRED, PNE_CORE_MISPREDBR_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_CORE_INSTR_DECODED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_CORE_INSTR_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_CORE_FP_COMPS_OP_EXE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_OPS, {0, {PNE_CORE_FP_COMPS_OP_EXE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_CORE_BR_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_VEC_INS,       {0, {PNE_PM_MMX_INSTR_EXEC,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},  Says event exists on P2 only  */
   {PAPI_RES_STL, {0, {PNE_CORE_RESOURCE_STALL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_CORE_UNHLTCORE_CYCLES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH, {DERIVED_SUB, {PNE_CORE_DATA_MEM_REF, PNE_CORE_DCACHE_REPL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_CORE_DATA_MEM_REF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_CORE_L2_LD_SELF_ANY_MESI, PNE_CORE_L2_ST_SELF_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_CORE_L2_LD_SELF_ANY_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCW, {0, {PNE_CORE_L2_ST_SELF_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICH, {DERIVED_SUB, {PNE_CORE_BUS_TRANS_IFETCH_SELF, PNE_PM_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICH,
    {DERIVED_SUB, {PNE_CORE_L2_IFETCH_SELF_MESI, PNE_CORE_BUS_TRANS_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_CORE_BUS_TRANS_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {0, {PNE_CORE_L2_IFETCH_SELF_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_CORE_BUS_TRANS_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICR, {0, {PNE_CORE_L2_IFETCH_SELF_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCH, {DERIVED_SUB, {PNE_CORE_L2_RQSTS_SELF_ANY_MESI, PNE_CORE_L2_LINES_IN_SELF_ANY, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_CORE_DATA_MEM_REF, PNE_CORE_BUS_TRANS_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCA, {0, {PNE_CORE_L2_RQSTS_SELF_ANY_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCR, {DERIVED_ADD, {PNE_CORE_L2_LD_SELF_ANY_MESI, PNE_CORE_L2_IFETCH_SELF_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCW, {0, {PNE_CORE_L2_ST_SELF_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FML_INS, {0, {PNE_CORE_MUL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FDV_INS, {0, {PNE_CORE_DIV, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

const hwi_search_t _papi_hwd_p2_preset_map[] = {
   {PAPI_L1_DCM, {0, {PNE_P2_DCU_LINES_IN, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICM, {0, {PNE_P2_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCM,
    {DERIVED_SUB, {PNE_P2_L2_LINES_IN, PNE_P2_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICM, {0, {PNE_P2_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {0, {PNE_P2_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCM, {0, {PNE_P2_L2_LINES_IN, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_SHR, {0, {PNE_P2_L2_RQSTS_S, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_CA_CLN, {0, {PNE_P2_BUS_TRAN_RFO_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
/*   { PAPI_CA_INV,        {0, { PNE_P2_BUS_HITM_DRV,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},   */
   {PAPI_CA_ITV, {0, {PNE_P2_BUS_TRAN_INVAL_SELF, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_P2_ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_P2_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_STM, {0, {PNE_P2_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_LDM, {DERIVED_SUB, {PNE_P2_L2_LINES_IN, PNE_P2_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_STM, {0, {PNE_P2_L2_M_LINES_INM, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BTAC_M, {0, {PNE_P2_BTB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_P2_HW_INT_RX, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_CN, {0, {PNE_P2_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_P2_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_NTK,
    {DERIVED_SUB, {PNE_P2_BR_INST_RETIRED, PNE_P2_BR_TAKEN_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_P2_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_PRC,
    {DERIVED_SUB, {PNE_P2_BR_INST_RETIRED, PNE_P2_BR_MISS_PRED_RETIRED, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_P2_INST_DECODED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_P2_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_P2_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FP_OPS, {0, {PNE_P2_FLOPS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_P2_BR_INST_RETIRED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_VEC_INS, {0, {PNE_P2_MMX_INSTR_EXEC, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_RES_STL, {0, {PNE_P2_RESOURCE_STALLS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_P2_CPU_CLK_UNHALTED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH, {DERIVED_SUB, {PNE_P2_DATA_MEM_REFS, PNE_P2_DCU_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_P2_DATA_MEM_REFS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_P2_L2_LD_MESI, PNE_P2_L2_ST_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_P2_L2_LD_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCW, {0, {PNE_P2_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICH, {DERIVED_SUB, {PNE_P2_IFU_IFETCH, PNE_P2_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICH,
    {DERIVED_SUB, {PNE_P2_L2_IFETCH_MESI, PNE_P2_BUS_TRAN_IFETCH_SELF, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_P2_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {0, {PNE_P2_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_P2_IFU_IFETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICR, {0, {PNE_P2_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCH, {DERIVED_SUB, {PNE_P2_L2_RQSTS_MESI, PNE_P2_L2_LINES_IN, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_P2_DATA_MEM_REFS, PNE_P2_IFU_IFETCH, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCA, {0, {PNE_P2_L2_RQSTS_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCR, {DERIVED_ADD, {PNE_P2_L2_LD_MESI, PNE_P2_L2_IFETCH_MESI, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCW, {0, {PNE_P2_L2_ST_MESI, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FML_INS, {0, {PNE_P2_MUL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FDV_INS, {0, {PNE_P2_DIV, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

const hwi_search_t _papi_hwd_ath_preset_map[] = {
   {PAPI_L1_DCM, {DERIVED_ADD, {PNE_ATH_SYS_DC_REFILLS_MOES, PNE_ATH_L2_DC_REFILLS_MOES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICM, {0, {PNE_ATH_IC_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCM, {0, {PNE_ATH_SYS_DC_REFILLS_MOES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICM, {0, {PNE_ATH_SYS_IC_REFILLS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {DERIVED_ADD, {PNE_ATH_SYS_DC_REFILLS_MOES, PNE_ATH_L2_DC_REFILLS_MOES, PNE_ATH_IC_MISSES, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCM,
    {DERIVED_ADD, {PNE_ATH_SYS_DC_REFILLS_MOES, PNE_ATH_SYS_IC_REFILLS, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_ATH_L1_AND_L2_DTLB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_ATH_L2_ITLB_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_TL,
    {DERIVED_ADD, {PNE_ATH_L1_AND_L2_DTLB_MISSES, PNE_ATH_L2_ITLB_MISSES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_ATH_L2_DC_REFILLS_OES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_STM, {0, {PNE_ATH_L2_DC_REFILLS_M, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_LDM, {0, {PNE_ATH_SYS_DC_REFILLS_OES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_STM, {0, {PNE_ATH_SYS_DC_REFILLS_M, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_ATH_TAKEN_HARDWARE_INTS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_UCN, {0, {PNE_ATH_RET_FAR_CONTROL_TRANSFERS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_CN, {0, {PNE_ATH_RET_BR, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_ATH_RET_TAKEN_BR, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_NTK, {DERIVED_SUB, {PNE_ATH_RET_BR, PNE_ATH_RET_TAKEN_BR, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_ATH_RET_BR_MIS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_PRC, {DERIVED_SUB, {PNE_ATH_RET_BR, PNE_ATH_RET_BR_MIS, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_ATH_RET_INSTRUCTIONS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_ATH_RET_TAKEN_BR, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
//   { PAPI_VEC_INS,           {0, { PNE_ATH_DCU_LINES_IN,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_RES_STL, {0, {PNE_ATH_ALL_QUIET_STALL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_ATH_TOT_CYC, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH, {DERIVED_POSTFIX, {PNE_ATH_DC_ACCESSES, PNE_ATH_SYS_DC_REFILLS_MOES, PNE_ATH_L2_DC_REFILLS_MOES, PAPI_NULL}, {"N0|N1|-|N2|-|",}}},
   {PAPI_L2_DCH, {0, {PNE_ATH_L2_DC_REFILLS_MOES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_ATH_DC_ACCESSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_ATH_SYS_DC_REFILLS_MOES, PNE_ATH_L2_DC_REFILLS_MOES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_ATH_L2_DC_REFILLS_OES, PAPI_NULL, PAPI_NULL, PAPI_NULL},{0,}}},
   {PAPI_L2_DCW, {0, {PNE_ATH_L2_DC_REFILLS_M, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_ATH_IC_FETCHES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {0, {PNE_ATH_IC_MISSES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_ATH_IC_FETCHES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_ATH_DC_ACCESSES, PNE_ATH_IC_FETCHES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

const hwi_search_t _papi_hwd_opt_preset_map[] = {
   {PAPI_L1_ICH, {DERIVED_POSTFIX, {PNE_OPT_IC_FETCH, PNE_OPT_IC_SYS_REFILL, PNE_OPT_IC_L2_REFILL, PAPI_NULL}, {"N0|N1|-|N2|-|",}}},
   {PAPI_L2_ICH, {0, {PNE_OPT_IC_L2_REFILL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCM, {DERIVED_ADD, {PNE_OPT_DC_SYS_REFILL_MOES, PNE_OPT_DC_L2_REFILL_MOES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICM, {DERIVED_ADD, {PNE_OPT_IC_L2_REFILL, PNE_OPT_IC_SYS_REFILL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCM, {0, {PNE_OPT_DC_SYS_REFILL_MOES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICM, {0, {PNE_OPT_IC_SYS_REFILL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCM, {DERIVED_ADD, {PNE_OPT_DC_SYS_REFILL_MOES, PNE_OPT_IC_SYS_REFILL,PNE_OPT_IC_L2_REFILL,PNE_OPT_DC_L2_REFILL_MOES},{0,}}},
   {PAPI_L2_TCM, {DERIVED_ADD, {PNE_OPT_DC_SYS_REFILL_MOES, PNE_OPT_IC_SYS_REFILL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FPU_IDL, {0, {PNE_OPT_FP_NONE_RET, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_OPT_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_OPT_IC_L1ITLB_MISS_AND_L2ITLB_MISS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TLB_TL, {DERIVED_ADD, {PNE_OPT_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,PNE_OPT_IC_L1ITLB_MISS_AND_L2ITLB_MISS,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_LDM, {0, {PNE_OPT_DC_L2_REFILL_OES,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_STM, {0, {PNE_OPT_DC_L2_REFILL_M,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_LDM, {0, {PNE_OPT_DC_SYS_REFILL_OES,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L2_STM, {0, {PNE_OPT_DC_SYS_REFILL_M,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_STL_ICY,{0, {PNE_OPT_FR_DECODER_EMPTY, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_HW_INT, {0, {PNE_OPT_FR_HW_INTS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_OPT_FR_BR_TAKEN, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_OPT_FR_BR_MIS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_OPT_FR_X86_INS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},

   // This definition give an accurate count of the instructions retired through the FP unit
   // It counts just about everything except MMX and 3DNow instructions
   // Unfortunately, it also counts loads and stores. Therefore the count will be uniformly
   // high, but proportional to the work done.
   {PAPI_FP_INS, {0, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},

   // This definition is speculative but gives good answers on our simple test cases
   // It overcounts FP operations, sometimes by A LOT, but doesn't count loads and stores
   {PAPI_FP_OPS, {0, {PNE_OPT_FP_MULT_AND_ADD_PIPE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},

   // These definitions try to correct high counting of retired flop events
   // by subtracting speculative loads and stores, which trend high
   // The resulting value therefore trends low, sometimes by A LOT
   // The first seems most appropriate for SINGLE precision operations;
//   {PAPI_FP_OPS, {DERIVED_SUB, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PNE_OPT_FP_ST_PIPE, PAPI_NULL, PAPI_NULL}, {0,}}},
   // The second works best for DOUBLE precision operations;
//   {PAPI_FP_OPS, {DERIVED_SUB, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PNE_OPT_FP_ST_PIPE_AND_LOAD, PAPI_NULL, PAPI_NULL}, {0,}}},

   {PAPI_BR_INS, {0, {PNE_OPT_FR_BR, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_VEC_INS, {0, {PNE_OPT_FR_FPU_SSE_SSE2_PACKED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_RES_STL, {0, {PNE_OPT_FR_DISPATCH_STALLS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_OPT_CPU_CLK_UNHALTED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_DCH,  {DERIVED_POSTFIX, {PNE_OPT_DC_ACCESS,PNE_OPT_DC_L2_REFILL_MOES, PNE_OPT_DC_SYS_REFILL_MOES,PAPI_NULL},{"N0|N1|-|N2|-|",}}},
   {PAPI_L2_DCH,  {0, {PNE_OPT_DC_L2_REFILL_MOES,PAPI_NULL,PAPI_NULL,PAPI_NULL},{0,}}},
   {PAPI_L1_DCA, {0, {PNE_OPT_DC_ACCESS, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCA, {DERIVED_ADD, {PNE_OPT_DC_SYS_REFILL_MOES, PNE_OPT_DC_L2_REFILL_MOES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCR, {0, {PNE_OPT_DC_L2_REFILL_OES, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_DCW, {0, {PNE_OPT_DC_L2_REFILL_M, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICA, {0, {PNE_OPT_IC_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_ICA, {DERIVED_ADD, {PNE_OPT_IC_L2_REFILL, PNE_OPT_IC_SYS_REFILL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_ICR, {0, {PNE_OPT_IC_FETCH, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCA, {DERIVED_ADD, {PNE_OPT_DC_ACCESS, PNE_OPT_IC_FETCH, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L2_TCA, {DERIVED_ADD, {PNE_OPT_IC_L2_REFILL, PNE_OPT_IC_SYS_REFILL, PNE_OPT_DC_L2_REFILL_MOES, PNE_OPT_DC_SYS_REFILL_MOES}, {0,}}},
   {PAPI_L2_TCH, {DERIVED_ADD, {PNE_OPT_IC_L2_REFILL, PNE_OPT_DC_L2_REFILL_MOES, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FML_INS, {0, {PNE_OPT_FP_MULT_PIPE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_FAD_INS, {0, {PNE_OPT_FP_ADD_PIPE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {PAPI_L1_TCH, {DERIVED_POSTFIX, {PNE_OPT_DC_ACCESS,PNE_OPT_IC_FETCH,PNE_OPT_DC_MISS,PNE_OPT_IC_MISS}, {"N0|N1|+|N2|-|N3|-|"}}},
   {0, {0, {PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}}
};

#if defined(PAPI_OPTERON_FP_RETIRED)
   #define FPU _papi_hwd_opt_FP_RETIRED
   #define FPU_DESC _papi_hwd_opt_FP_RETIRED_dev_notes
#elif defined(PAPI_OPTERON_FP_SSE_SP)
   #define FPU _papi_hwd_opt_FP_SSE_SP
   #define FPU_DESC _papi_hwd_opt_FP_SSE_SP_dev_notes
#elif defined(PAPI_OPTERON_FP_SSE_DP)
   #define FPU _papi_hwd_opt_FP_SSE_DP
   #define FPU_DESC _papi_hwd_opt_FP_SSE_DP_dev_notes
#else
   #define FPU _papi_hwd_opt_FP_SPECULATIVE
   #define FPU_DESC _papi_hwd_opt_FP_SPECULATIVE_dev_notes
#endif

/* Table defining PAPI_FP_OPS as all ops retired */
hwi_search_t _papi_hwd_opt_FP_RETIRED[] = {
   {PAPI_FP_OPS, {0, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

/* Table defining PAPI_FP_OPS as all ops retired minus one type of speculative store */
hwi_search_t _papi_hwd_opt_FP_SSE_SP[] = {
   {PAPI_FP_OPS, {DERIVED_SUB, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PNE_OPT_FP_ST_PIPE, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

/* Table defining PAPI_FP_OPS as all ops retired minus two types of speculative stores */
hwi_search_t _papi_hwd_opt_FP_SSE_DP[] = {
   {PAPI_FP_OPS, {DERIVED_SUB, {PNE_OPT_FR_FPU_X87_SSE_SSE2_SCALAR_PACKED, PNE_OPT_FP_ST_PIPE_AND_LOAD, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

/* Table defining PAPI_FP_OPS as speculative multiplys and adds */
hwi_search_t _papi_hwd_opt_FP_SPECULATIVE[] = {
   {PAPI_FP_OPS, {0, {PNE_OPT_FP_MULT_AND_ADD_PIPE, PAPI_NULL, PAPI_NULL, PAPI_NULL}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

/* These are examples of dense developer notes arrays. Each consists of an array
   of structures containing an event and a note string. Pointers to these strings 
   are inserted into a sparse event description structure at init time. This allows
   the use of rare developer strings with no string copies and very little space
   wasted on unused structure elements.
*/
const hwi_dev_notes_t _papi_hwd_opt_FP_RETIRED_dev_notes[] = {
/* preset, note */
   {PAPI_FP_OPS, "Counts all retired floating point operations, including data movement. Precise, and proportional to work done, but much higher than theoretical."},
   {0, NULL}
};

const hwi_dev_notes_t _papi_hwd_opt_FP_SPECULATIVE_dev_notes[] = {
/* preset, note */
   {PAPI_FP_OPS, "Counts speculative adds and multiplies. Variable and higher than theoretical."},
   {0, NULL}
};

const hwi_dev_notes_t _papi_hwd_opt_FP_SSE_SP_dev_notes[] = {
/* preset, note */
   {PAPI_FP_OPS, "Counts retired ops corrected for data motion. Optimized for single precision; lower than theoretical."},
   {0, NULL}
};

const hwi_dev_notes_t _papi_hwd_opt_FP_SSE_DP_dev_notes[] = {
/* preset, note */
   {PAPI_FP_OPS, "Counts retired ops corrected for data motion. Optimized for double precision; lower than theoretical."},
   {0, NULL}
};

/* The following are the (huge) native tables.  They contain the 
   following:
   A short text description of the native event,
   A longer more descriptive text of the native event,
   Information on which counter the native can live,
   and the Native Event Code.
   In some cases, event codes can be programmatically expanded to
   include MESI or MOESI bits. These are identified by the addition
   of a HAS_MESI or HAS_MOESI flag in the selector field.               */
/* The notes/descriptions of these events have sometimes been truncated */
/* Please see the architecture's manual for any clarifications.         */

const int _papi_hwd_p3_native_count = (PNE_P3_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_p3_native_map[] = {
   {"DATA_MEM_REFS",
    "All loads/stores from/to any memory type",
    {CNTRS12, 0x43}},
   {"DCU_LINES_IN",
    "Total lines allocated in the DCU",
    {CNTRS12, 0x45}},
   {"DCU_M_LINES_IN",
    "Number of M state lines allocated in the DCU",
    {CNTRS12, 0x46}},
   {"DCU_M_LINES_OUT",
    "Number of M state lines evicted from the DCU",
    {CNTRS12, 0x47}},
   {"DCU_MISS_OUTSTANDING",
    "Weighted no. of cycles while a DCU miss is outstanding, incremented by the no. of outstanding cache misses at any particular time",
    {CNTRS12, 0x48}},
   {"IFU_IFETCH",
    "Number of instruction fetches, both cacheable and noncacheable, including UC fetches",
    {CNTRS12, 0x80}},
   {"IFU_IFETCH_MISS",
    "Number of instruction fetch misses including UC accesses",
    {CNTRS12, 0x81}},
   {"ITLB_MISS",
    "Number of ITLB misses",
    {CNTRS12, 0x85}},
   {"IFU_MEM_STALL",
    "Number of cycles instruction fetch is stalled, for any reason, including IFU cache misses, ITLB misses, ITLB faults, and other minor stalls",
    {CNTRS12, 0x86}},
   {"ILD_STALL",
    "Number of cycles the instruction length decoder is stalled",
    {CNTRS12, 0x87}},

   {"L2_IFETCH",
    "Number of fetches from a line of L2 instruction cache",
    {CNTRS12 | HAS_MESI, 0x28}},
   {"L2_LD",
    "Number of loads from a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x29}},
   {"L2_ST",
    "Number of stores to a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x2a}},
   {"L2_RQSTS",
    "Total number of L2 requests to a line",
    {CNTRS12 | HAS_MESI, 0x2e}},

   {"L2_LINES_IN",
    "Number of lines allocated in the L2",
    {CNTRS12, 0x24}},
   {"L2_LINES_OUT",
    "Number of lines removed fromo the L2 for any reason",
    {CNTRS12, 0x26}},
   {"L2_M_LINES_INM",
    "Number of modified lines allocated in the L2",
    {CNTRS12, 0x25}},
   {"L2_M_LINES_OUTM",
    "Number of modified lines removed from the L2 for any reason",
    {CNTRS12, 0x27}},
   {"L2_ADS",
    "Number of L2 address strobes",
    {CNTRS12, 0x21}},
   {"L2_DBS_BUSY",
    "Number of cycles the L2 cache data bus was busy",
    {CNTRS12, 0x22}},
   {"L2_DBS_BUSY_RD",
    "Number of cycles the data bus was busy transferring read data from the L2 to the processor",
    {CNTRS12, 0x23}},
   {"BUS_DRDY_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving DRDY#",
    {CNTRS12, 0x62}},
   {"BUS_DRDY_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving DRDY#",
    {CNTRS12, 0x2062}},
   {"BUS_LOCK_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving LOCK#",
    {CNTRS12, 0x63}},
   {"BUS_LOCK_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving LOCK#",
    {CNTRS12, 0x2063}},
   {"BUS_REQ_OUTSTANDING",
    "Number of bus outstanding bus requests",
    {CNTRS12, 0x60}},
   {"BUS_TRAN_BRD_SELF",
    "Number of burst read transactions by the processor",
    {CNTRS12, 0x65}},
   {"BUS_TRAN_BRD_ANY",
    "Number of burst read transactions by any agent",
    {CNTRS12, 0x2065}},
   {"BUS_TRAN_RFO_SELF",
    "Number of completed read for ownership transactions by the processor",
    {CNTRS12, 0x66}},
   {"BUS_TRAN_RFO_ANY",
    "Number of completed read for ownership transactions by any agent",
    {CNTRS12, 0x2066}},
   {"BUS_TRANS_WB_SELF",
    "Number of completed write back transactions by the processor",
    {CNTRS12, 0x67}},
   {"BUS_TRANS_WB_ANY",
    "Number of completed write back transactions by any agent",
    {CNTRS12, 0x2067}},
   {"BUS_TRAN_IFETCH_SELF",
    "Number of completed instruction fetch transactions by the processor",
    {CNTRS12, 0x68}},
   {"BUS_TRAN_IFETCH_ANY",
    "Number of completed instruction fetch transactions by any agent",
    {CNTRS12, 0x2068}},
   {"BUS_TRAN_INVAL_SELF",
    "Number of completed invalidate transactions by the processor",
    {CNTRS12, 0x69}},
   {"BUS_TRAN_INVAL_ANY",
    "Number of completed invalidate transactions by any agent",
    {CNTRS12, 0x2069}},
   {"BUS_TRAN_PWR_SELF",
    "Number of completed partial write transactions by the processor",
    {CNTRS12, 0x6a}},
   {"BUS_TRAN_PWR_ANY",
    "Number of completed partial write transactions by any agent",
    {CNTRS12, 0x206a}},
   {"BUS_TRANS_P_SELF",
    "Number of completed partial transactions by the processor",
    {CNTRS12, 0x6b}},
   {"BUS_TRANS_P_ANY",
    "Number of completed partial transactions by any agent",
    {CNTRS12, 0x206b}},
   {"BUS_TRANS_IO_SELF",
    "Number of completed I/O transactions by the processor",
    {CNTRS12, 0x6c}},
   {"BUS_TRANS_IO_ANY",
    "Number of completed I/O transactions by any agent",
    {CNTRS12, 0x206c}},
   {"BUS_TRAN_DEF_SELF",
    "Number of completed deferred transactions by the processor",
    {CNTRS12, 0x6d}},
   {"BUS_TRAN_DEF_ANY",
    "Number of completed deferred transactions by any agent",
    {CNTRS12, 0x206d}},
   {"BUS_TRAN_BURST_SELF",
    "Number of completed burst transactions by the processor",
    {CNTRS12, 0x6e}},
   {"BUS_TRAN_BURST_ANY",
    "Number of completed burst transactions by any agent",
    {CNTRS12, 0x206e}},
   {"BUS_TRAN_ANY_SELF",
    "Number of completed bus transactions by the processor",
    {CNTRS12, 0x70}},
   {"BUS_TRAN_ANY_ANY",
    "Number of completed bus transactions by any agent",
    {CNTRS12, 0x2070}},
   {"BUS_TRAN_MEM_SELF",
    "Number of completed memory transactions by the processor",
    {CNTRS12, 0x6f}},
   {"BUS_TRAN_MEM_ANY",
    "Number of completed memory transactions by any agent",
    {CNTRS12, 0x206f}},
   {"BUS_DATA_RCV",
    "Number of bus clock cycles during which this processor is receiving data",
    {CNTRS12, 0x64}},
   {"BUS_BNR_DRV",
    "Number of bus clock cycles during which this processor is driving the BNR# pin",
    {CNTRS12, 0x61}},
   {"BUS_HIT_DRV",
    "Number of bus clock cycles during which this processor is driving the HIT# pin",
    {CNTRS12, 0x7a}},
   {"BUS_HITM_DRV",
    "Number of bus clock cycles during which this processor is driving the HITM# pin",
    {CNTRS12, 0x7b}},
   {"BUS_SNOOP_STALL",
    "Number of clock cycles during which the bus is snoop stalled",
    {CNTRS12, 0x7e}},
   {"FLOPS",
    "Number of computational floating-point operations retired",
    {CNTR1, 0xc1}},
   {"FP_COMP_OPS_EXE",
    "Number of computational floating-point operations executed",
    {CNTR1, 0x10}},
   {"FP_ASSIST",
    "Number of floating-point exception cases handled by microcode",
    {CNTR2, 0x11}},
   {"MUL",
    "Number of integer and floating point multiplies",
    {CNTR2, 0x12}},
   {"DIV",
    "Number of integer and floating point divides",
    {CNTR2, 0x13}},
   {"CYCLES_DIV_BUSY",
    "Number of cycles during which the divider is busy and cannot accept new divides",
    {CNTR1, 0x14}},
   {"LD_BLOCKS",
    "Number of load operations delayed due to store buffer blocks",
    {CNTRS12, 0x3}},
   {"SB_DRAINS",
    "Number of store buffer drain cycles",
    {CNTRS12, 0x4}},
   {"MISALIGN_MEM_REF",
    "Number of misaligned data memory references",
    {CNTRS12, 0x5}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_NTA",
    "Number of Streaming SIMD extensions prefetch NTA dispatched",
    {CNTRS12, 0x7}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_T1",
    "Number of Streaming SIMD extensions prefetch T1 dispatched",
    {CNTRS12, 0x107}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_T2",
    "Number of Streaming SIMD extensions prefetch T2 dispatched",
    {CNTRS12, 0x207}},
   {"EMON_KNI_PREF_DISPATCHED_WEAKLY_ORDERED_STORES",
    "Number of Streaming SIMD extensions prefetch weakly ordered stores dispatched",
    {CNTRS12, 0x307}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_NTA",
    "Number of prefetch NTA instructions that miss all caches",
    {CNTRS12, 0x4b}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_T1",
    "Number of prefetch T1instructions that miss all caches",
    {CNTRS12, 0x14b}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_T2",
    "Number of prefetch T2 instructions that miss all caches",
    {CNTRS12, 0x24b}},
   {"EMON_KNI_PREF_MISS_WEAKLY_ORDERED_STORES",
    "Number of weakly-ordered instructions that miss all caches",
    {CNTRS12, 0x34b}},
   {"INST_RETIRED",
    "Number of instructions retired",
    {CNTRS12, 0xc0}},
   {"UOPS_RETIRED",
    "Number of uops retired",
    {CNTRS12, 0xc2}},
   {"INST_DECODED",
    "Number of instructions decoded",
    {CNTRS12, 0xd0}},
   {"EMON_KNI_INST_RETIRED_PACKED_AND_SCALAR",
    "Number of packed and scalar Streaming SIMD extensions retired",
    {CNTRS12, 0xd8}},
   {"EMON_KNI_INST_RETIRED_SCALAR",
    "Number of scalar Streaming SIMD extensions retired",
    {CNTRS12, 0x1d8}},
   {"EMON_KNI_COMP_INST_RET_PACKED_AND_SCALAR",
    "Number of packed and scalar Straming SIMD computation instructions retired",
    {CNTRS12, 0xd9}},
   {"EMON_KNI_COMP_INST_RET_SCALAR",
    "Number of scalar Straming SIMD computation instructions retired",
    {CNTRS12, 0x1d9}},
   {"HW_INT_RX",
    "Number of hardware interrupts received",
    {CNTRS12, 0xc8}},
   {"CYCLES_INT_MASKED",
    "Number of processor cycles to which interrupts are enabled",
    {CNTRS12, 0xc6}},
   {"CYCLES_INT_PENDING_AND_MASKED",
    "Number of processor cycles for which interrupts are disabled and interrupts are pending",
    {CNTRS12, 0xc7}},
   {"BR_INST_RETIRED",
    "Number of branch instructions retired",
    {CNTRS12, 0xc4}},
   {"BR_MISS_PRED_RETIRED",
    "Number of mispredicted branches retired",
    {CNTRS12, 0xc5}},
   {"BR_TAKEN_RETIRED",
    "Number of taken branches retired",
    {CNTRS12, 0xc9}},
   {"BR_MISS_PRED_TAKEN_RET",
    "Number of mispredictions branches retired",
    {CNTRS12, 0xca}},
   {"BR_INST_DECODED",
    "Number of branch instructions decoded",
    {CNTRS12, 0xe0}},
   {"BTB_MISSES",
    "Number of branches for which the BTB did not produce a prediction",
    {CNTRS12, 0xe2}},
   {"BR_BOGUS",
    "Number of bogus branches",
    {CNTRS12, 0xe4}},
   {"BACLEARS",
    "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not",
    {CNTRS12, 0xe6}},
   {"RESOURCE_STALLS",
    "Incremented by 1 during every cycle for which there is a resource related stall",
    {CNTRS12, 0xa2}},
   {"PARTIAL_RAT_STALLS",
    "Number of cycles or events for partial stalls.  Includes flag partial stalls",
    {CNTRS12, 0xd2}},
   {"SEGMENT_REG_LOADS",
    "Number of segment register loads",
    {CNTRS12, 0x06}},
   {"CPU_CLK_UNHALTED",
    "Number of cycles during which the processor is not halted",
    {CNTRS12, 0x79}},
   {"MMX_SAT_INSTR_EXEC",
    "Number of MMX Saturating instructions executed",
    {CNTRS12, 0xb1}},
   {"MMX_UOPS_EXEC",
    "Number of MMX uops executed",
    {CNTRS12, 0xfb2}},
   {"MMX_INSTR_TYPE_EXEC_MUL",
    "Number of MMX packed multiply instructions executed",
    {CNTRS12, 0x1b3}},
   {"MMX_INSTR_TYPE_EXEC_SHIFT",
    "Number of MMX packed shift instructions executed",
    {CNTRS12, 0x2b3}},
   {"MMX_INSTR_TYPE_EXEC_PACK_OPS",
    "Number of MMX pack operation instructions executed",
    {CNTRS12, 0x4b3}},
   {"MMX_INSTR_TYPE_EXEC_UNPACK_OPS",
    "Number of MMX unpack operation instructions executed",
    {CNTRS12, 0x8b3}},
   {"MMX_INSTR_TYPE_EXEC_LOGICAL",
    "Number of MMX packed logical instructions executed",
    {CNTRS12, 0x10b3}},
   {"MMX_INSTR_TYPE_EXEC_ARITHMETIC",
    "Number of MMX packed arithmetic instructions executed",
    {CNTRS12, 0x20b3}},
   {"FP_MMX_TRANS_MMX_TO_FP",
    "Transitions from MMX instruction to floating-point instructions",
    {CNTRS12, 0xcc}},
   {"FP_MMX_TRANS_FP_TO_MMX",
    "Transitions from floating-point instructions to MMX instructions",
    {CNTRS12, 0x1cc}},
   {"MMX_ASSIST",
    "Number of MMX Assists, ie the number of EMMS instructions executed",
    {CNTRS12, 0xcd}},
   {"SEG_RENAME_STALLS_ES",
    "Number of Segment Register ES Renaming stalls",
    {CNTRS12, 0x1d4}},
   {"SEG_RENAME_STALLS_DS",
    "Number of Segment Register DS Renaming stalls",
    {CNTRS12, 0x2d4}},
   {"SEG_RENAME_STALLS_FS",
    "Number of Segment Register FS Renaming stalls",
    {CNTRS12, 0x4d4}},
   {"SEG_RENAME_STALLS_GS",
    "Number of Segment Register GS Renaming stalls",
    {CNTRS12, 0x8d4}},
   {"SEG_RENAME_STALLS_TOT",
    "Total Number of Segment Register Renaming stalls",
    {CNTRS12, 0xfd4}},
   {"SEG_REG_RENAMES_ES",
    "Number of Segment Register ES Renames",
    {CNTRS12, 0x1d5}},
   {"SEG_REG_RENAMES_DS",
    "Number of Segment Register DS Renames",
    {CNTRS12, 0x2d5}},
   {"SEG_REG_RENAMES_FS",
    "Number of Segment Register FS Renames",
    {CNTRS12, 0x4d5}},
   {"SEG_REG_RENAMES_GS",
    "Number of Segment Register GS Renames",
    {CNTRS12, 0x8d5}},
   {"SEG_REG_RENAMES_TOT",
    "Total number of Segment Register Renames",
    {CNTRS12, 0xfd5}},
   {"RET_SEG_RENAMES",
    "Number of segment register rename events retired",
    {CNTRS12, 0xd6}},
   {"", "", {0, 0}}
};

const int _papi_hwd_pm_native_count = (PNE_PM_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_pm_native_map[] = {
   {"DATA_MEM_REFS",
    "All loads/stores from/to any memory type",
    {CNTRS12, 0x43}},
   {"DCU_LINES_IN",
    "Total lines allocated in the DCU",
    {CNTRS12, 0x45}},
   {"DCU_M_LINES_IN",
    "Number of M state lines allocated in the DCU",
    {CNTRS12, 0x46}},
   {"DCU_M_LINES_OUT",
    "Number of M state lines evicted from the DCU",
    {CNTRS12, 0x47}},
   {"DCU_MISS_OUTSTANDING",
    "Weighted no. of cycles while a DCU miss is outstanding, incremented by the no. of outstanding cache misses at any particular time",
    {CNTRS12, 0x48}},
   {"IFU_IFETCH",
    "Number of instruction fetches, both cacheable and noncacheable, including UC fetches",
    {CNTRS12, 0x80}},
   {"IFU_IFETCH_MISS",
    "Number of instruction fetch misses including UC accesses",
    {CNTRS12, 0x81}},
   {"ITLB_MISS",
    "Number of ITLB misses",
    {CNTRS12, 0x85}},
   {"IFU_MEM_STALL",
    "Number of cycles instruction fetch is stalled, for any reason, including IFU cache misses, ITLB misses, ITLB faults, and other minor stalls",
    {CNTRS12, 0x86}},
   {"ILD_STALL",
    "Number of cycles the instruction length decoder is stalled",
    {CNTRS12, 0x87}},

   {"L2_IFETCH",
    "Number of fetches from a modified line of L2 instruction cache",
    {CNTRS12 | HAS_MESI, 0x28}},
   {"L2_LD",
    "Number of loads from a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x29}},

   {"L2_LD_HWD_PREFETCHED",
    "Number of loads from an hardware-prefetched line of the L2 data cache",
    {CNTRS12, 0x1029}},
   {"L2_LD_TOT",
    "Total number of L2 data loads",
    {CNTRS12, 0x2029}},

   {"L2_ST",
    "Number of stores to a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x2a}},
   {"L2_LINES_IN",
    "Number of lines allocated in the L2 cache",
    {CNTRS12 | HAS_MESI, 0x24}},

   {"L2_HWD_PREFETCHED_LINES_IN",
    "Number of hardware-prefetched lines allocated in the L2 cache",
    {CNTRS12, 0x1024}},
   {"L2_TOT_LINES_IN",
    "Total number of lines allocated in the L2",
    {CNTRS12, 0x2024}},

   {"L2_LINES_OUT",
    "Number of lines evicted from the L2 cache",
    {CNTRS12 | HAS_MESI, 0x26}},

   {"L2_HWD_PREFETCHED_LINES_OUT",
    "Number of hardware-prefetched lines evicted from the L2 cache",
    {CNTRS12, 0x1026}},
   {"L2_TOT_LINES_OUT",
    "Total number of lines evicted from the L2",
    {CNTRS12, 0x2026}},
   {"L2_M_LINES_INM",
    "Number of modified lines allocated in the L2",
    {CNTRS12, 0x25}},

   {"L2_M_LINES_OUT",
    "Number of M-state lines evicted from the L2 cache",
    {CNTRS12 | HAS_MESI, 0x27}},

   {"L2_HWD_PREFETCHED_M_LINES_OUT",
    "Number of hardware-prefetched M-state lines evicted from the L2 cache",
    {CNTRS12, 0x1027}},
   {"L2_TOT_M_LINES_OUT",
    "Total number of M-state lines evicted from the L2 cache",
    {CNTRS12, 0x2027}},

   {"L2_RQSTS",
    "Total number of L2 requests to a line",
    {CNTRS12 | HAS_MESI, 0x2e}},

   {"L2_ADS",
    "Number of L2 address strobes",
    {CNTRS12, 0x21}},
   {"L2_DBS_BUSY",
    "Number of cycles the L2 cache data bus was busy",
    {CNTRS12, 0x22}},
   {"L2_DBS_BUSY_RD",
    "Number of cycles the data bus was busy transferring read data from the L2 to the processor",
    {CNTRS12, 0x23}},
   {"BUS_DRDY_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving DRDY#",
    {CNTRS12, 0x62}},
   {"BUS_DRDY_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving DRDY#",
    {CNTRS12, 0x2062}},
   {"BUS_LOCK_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving LOCK#",
    {CNTRS12, 0x63}},
   {"BUS_LOCK_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving LOCK#",
    {CNTRS12, 0x2063}},
   {"BUS_REQ_OUTSTANDING",
    "Number of bus outstanding bus requests",
    {CNTRS12, 0x60}},
   {"BUS_TRAN_BRD_SELF",
    "Number of burst read transactions by the processor",
    {CNTRS12, 0x65}},
   {"BUS_TRAN_BRD_ANY",
    "Number of burst read transactions by any agent",
    {CNTRS12, 0x2065}},
   {"BUS_TRAN_RFO_SELF",
    "Number of completed read for ownership transactions by the processor",
    {CNTRS12, 0x66}},
   {"BUS_TRAN_RFO_ANY",
    "Number of completed read for ownership transactions by any agent",
    {CNTRS12, 0x2066}},
   {"BUS_TRANS_WB_SELF",
    "Number of completed write back transactions by the processor",
    {CNTRS12, 0x67}},
   {"BUS_TRANS_WB_ANY",
    "Number of completed write back transactions by any agent",
    {CNTRS12, 0x2067}},
   {"BUS_TRAN_IFETCH_SELF",
    "Number of completed instruction fetch transactions by the processor",
    {CNTRS12, 0x68}},
   {"BUS_TRAN_IFETCH_ANY",
    "Number of completed instruction fetch transactions by any agent",
    {CNTRS12, 0x2068}},
   {"BUS_TRAN_INVAL_SELF",
    "Number of completed invalidate transactions by the processor",
    {CNTRS12, 0x69}},
   {"BUS_TRAN_INVAL_ANY",
    "Number of completed invalidate transactions by any agent",
    {CNTRS12, 0x2069}},
   {"BUS_TRAN_PWR_SELF",
    "Number of completed partial write transactions by the processor",
    {CNTRS12, 0x6a}},
   {"BUS_TRAN_PWR_ANY",
    "Number of completed partial write transactions by any agent",
    {CNTRS12, 0x206a}},
   {"BUS_TRANS_P_SELF",
    "Number of completed partial transactions by the processor",
    {CNTRS12, 0x6b}},
   {"BUS_TRANS_P_ANY",
    "Number of completed partial transactions by any agent",
    {CNTRS12, 0x206b}},
   {"BUS_TRANS_IO_SELF",
    "Number of completed I/O transactions by the processor",
    {CNTRS12, 0x6c}},
   {"BUS_TRANS_IO_ANY",
    "Number of completed I/O transactions by any agent",
    {CNTRS12, 0x206c}},
   {"BUS_TRAN_DEF_SELF",
    "Number of completed deferred transactions by the processor",
    {CNTRS12, 0x6d}},
   {"BUS_TRAN_DEF_ANY",
    "Number of completed deferred transactions by any agent",
    {CNTRS12, 0x206d}},
   {"BUS_TRAN_BURST_SELF",
    "Number of completed burst transactions by the processor",
    {CNTRS12, 0x6e}},
   {"BUS_TRAN_BURST_ANY",
    "Number of completed burst transactions by any agent",
    {CNTRS12, 0x206e}},
   {"BUS_TRAN_ANY_SELF",
    "Number of completed bus transactions by the processor",
    {CNTRS12, 0x70}},
   {"BUS_TRAN_ANY_ANY",
    "Number of completed bus transactions by any agent",
    {CNTRS12, 0x2070}},
   {"BUS_TRAN_MEM_SELF",
    "Number of completed memory transactions by the processor",
    {CNTRS12, 0x6f}},
   {"BUS_TRAN_MEM_ANY",
    "Number of completed memory transactions by any agent",
    {CNTRS12, 0x206f}},
   {"BUS_DATA_RCV",
    "Number of bus clock cycles during which this processor is receiving data",
    {CNTRS12, 0x64}},
   {"BUS_BNR_DRV",
    "Number of bus clock cycles during which this processor is driving the BNR# pin",
    {CNTRS12, 0x61}},
   {"BUS_HIT_DRV",
    "Number of bus clock cycles during which this processor is driving the HIT# pin",
    {CNTRS12, 0x7a}},
   {"BUS_HITM_DRV",
    "Number of bus clock cycles during which this processor is driving the HITM# pin",
    {CNTRS12, 0x7b}},
   {"BUS_SNOOP_STALL",
    "Number of clock cycles during which the bus is snoop stalled",
    {CNTRS12, 0x7e}},
   {"FLOPS",
    "Number of computational floating-point operations retired",
    {CNTR1, 0xc1}},
   {"FP_COMP_OPS_EXE",
    "Number of computational floating-point operations executed",
    {CNTR1, 0x10}},
   {"FP_ASSIST",
    "Number of floating-point exception cases handled by microcode",
    {CNTR2, 0x11}},
   {"MUL",
    "Number of integer and floating point multiplies",
    {CNTR2, 0x12}},
   {"DIV",
    "Number of integer and floating point divides",
    {CNTR2, 0x13}},
   {"CYCLES_DIV_BUSY",
    "Number of cycles during which the divider is busy and cannot accept new divides",
    {CNTR1, 0x14}},
   {"LD_BLOCKS",
    "Number of load operations delayed due to store buffer blocks",
    {CNTRS12, 0x3}},
   {"SB_DRAINS",
    "Number of store buffer drain cycles",
    {CNTRS12, 0x4}},
   {"MISALIGN_MEM_REF",
    "Number of misaligned data memory references",
    {CNTRS12, 0x5}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_NTA",
    "Number of Streaming SIMD extensions prefetch NTA dispatched",
    {CNTRS12, 0x7}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_T1",
    "Number of Streaming SIMD extensions prefetch T1 dispatched",
    {CNTRS12, 0x107}},
   {"EMON_KNI_PREF_DISPATCHED_PREFETCHED_T2",
    "Number of Streaming SIMD extensions prefetch T2 dispatched",
    {CNTRS12, 0x207}},
   {"EMON_KNI_PREF_DISPATCHED_WEAKLY_ORDERED_STORES",
    "Number of Streaming SIMD extensions prefetch weakly ordered stores dispatched",
    {CNTRS12, 0x307}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_NTA",
    "Number of prefetch NTA instructions that miss all caches",
    {CNTRS12, 0x4b}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_T1",
    "Number of prefetch T1instructions that miss all caches",
    {CNTRS12, 0x14b}},
   {"EMON_KNI_PREF_MISS_PREFETCHED_T2",
    "Number of prefetch T2 instructions that miss all caches",
    {CNTRS12, 0x24b}},
   {"EMON_KNI_PREF_MISS_WEAKLY_ORDERED_STORES",
    "Number of weakly-ordered instructions that miss all caches",
    {CNTRS12, 0x34b}},
   {"INST_RETIRED",
    "Number of instructions retired",
    {CNTRS12, 0xc0}},
   {"UOPS_RETIRED",
    "Number of uops retired",
    {CNTRS12, 0xc2}},
   {"INST_DECODED",
    "Number of instructions decoded",
    {CNTRS12, 0xd0}},
   {"EMON_SSE_SSE2_INST_RETIRED_PACKED_AND_SCALAR_SINGLE",
    "Number of SSE packed single and scalar single Streaming SIMD extensions retired",
    {CNTRS12, 0xd8}},
   {"EMON_SSE_SSE2_INST_RETIRED_SCALAR_SINGLE",
    "Number of SSE scalar single Streaming SIMD extensions retired",
    {CNTRS12, 0x1d8}},
   {"EMON_SSE_SSE2_INST_RETIRED_PACKED_DOUBLE",
    "Number of SSE2 packed-double Streaming SIMD extensions retired",
    {CNTRS12, 0x2d8}},
   {"EMON_SSE_SSE2_INST_RETIRED_SCALAR_DOUBLE",
    "Number of SSE2 scalar-double Streaming SIMD extensions retired",
    {CNTRS12, 0x3d8}},
   {"EMON_SSE_SSE2_COMP_INST_RETIRED_PACKED_SINGLE",
    "Number of SSE packed single computational instructions retired",
    {CNTRS12, 0xd9}},
   {"EMON_SSE_SSE2_COMP_INST_RETIRED_SCALAR_SINGLE",
    "Number of SSE scalar single computational instructions retired",
    {CNTRS12, 0x1d9}},
   {"EMON_SSE_SSE2_COMP_INST_RETIRED_PACKED_DOUBLE",
    "Number of SSE2 packed double computational instructions retired",
    {CNTRS12, 0x2d9}},
   {"EMON_SSE_SSE2_COMP_INST_RETIRED_SCALAR_DOUBLE",
    "Number of SSE2 scalar double computational instructions retired",
    {CNTRS12, 0x3d9}},
   {"EMON_EST_TRANS",
    "Total number of Enhanced Intel SpeedStep technology transitions",
    {CNTRS12, 0x58}},
   {"EMON_EST_TRANS_FREQ",
    "Number of Enhanced Intel SpeedStep technology frequency transitions",
    {CNTRS12, 0x258}},
   {"EMON_THERMAL_TRIP",
    "Duration-Occurrences in thermal trip; to count number of thermal trips: bit 22 in PerfEvtSel0:1 needs to be set to enable edge detect",
    {CNTRS12, 0x59}},
   {"EMON_SIMD_INSTR_RETIRED",
    "Number of retired MMX instructions",
    {CNTRS12, 0xce}},
   {"EMON_SYNCH_UOPS",
    "Number of sync micro-ops",
    {CNTRS12, 0xd3}},
   {"EMON_ESP_UOPS",
    "Total number of micro-ops",
    {CNTRS12, 0xd7}},
   {"EMON_FUSED_UOPS_RET",
    "Total number of retired fused micro-ops",
    {CNTRS12, 0xda}},
   {"EMON_FUSED_UOPS_RET_LD_ONLY",
    "Number of retired fused only-load + op micro-ops",
    {CNTRS12, 0x1da}},
   {"EMON_FUSED_UOPS_RET_STD_ONLY",
    "Number of retired fused only-std + sta micro-ops",
    {CNTRS12, 0x2da}},
   {"EMON_UNFUSION",
    "Number of unfusion events in the ROB, happened on a FP execution to a fused uOp",
    {CNTRS12, 0xdb}},
   {"EMON_PREF_RQSTS_UP",
    "Number of upward prefetches issued",
    {CNTRS12, 0xf0}},
   {"EMON_PREF_RQSTS_DN",
    "Number of downward prefetches issued",
    {CNTRS12, 0xf8}},
   {"HW_INT_RX",
    "Number of hardware interrupts received",
    {CNTRS12, 0xc8}},
   {"CYCLES_INT_MASKED",
    "Number of processor cycles to which interrupts are enabled",
    {CNTRS12, 0xc6}},
   {"CYCLES_INT_PENDING_AND_MASKED",
    "Number of processor cycles for which interrupts are disabled and interrupts are pending",
    {CNTRS12, 0xc7}},
   {"BR_INST_EXEC",
    "Number of branch instructions executed (not necissarily retired)",
    {CNTRS12, 0x88}},
   {"BR_MISSP_EXEC",
    "Number of branch instructions executed that were mispredicted at execution",
    {CNTRS12, 0x89}},
   {"BR_BAC_MISSP_EXEC",
    "Number of branch instructions executed that were mispredicted at Front End (BAC)",
    {CNTRS12, 0x8a}},
   {"BR_CND_EXEC",
    "Number of conditional branch instructions executed",
    {CNTRS12, 0x8b}},
   {"BR_CND_MISSP_EXEC",
    "Number of conditional branch instructions executed that were mispredicted",
    {CNTRS12, 0x8c}},
   {"BR_IND_EXEC",
    "Number of indirect branch instructions executed",
    {CNTRS12, 0x8d}},
   {"BR_IND_MISSP_EXEC",
    "Number of indirect branch instructions executed that were mispredicted",
    {CNTRS12, 0x8e}},
   {"BR_RET_EXEC",
    "Number of return branch instructions executed",
    {CNTRS12, 0x8f}},
   {"BR_RET_MISSP_EXEC",
    "Number of return branch instructions executed that were mispredicted at execution",
    {CNTRS12, 0x90}},
   {"BR_RET_BAC_MISSP_EXEC",
    "Number of return branch instructions executed that were mispredicted at Front End (BAC)",
    {CNTRS12, 0x91}},
   {"BR_CALL_EXEC",
    "Number of CALL instructions executed",
    {CNTRS12, 0x92}},
   {"BR_CALL_MISSP_EXEC",
    "Number of CALL instructions executed and mispredicted",
    {CNTRS12, 0x93}},
   {"BR_IND_CALL_EXEC",
    "Number of indirect CALL instructions executed",
    {CNTRS12, 0x94}},
   {"BR_INST_RETIRED",
    "Number of branch instructions retired",
    {CNTRS12, 0xc4}},
   {"BR_MISS_PRED_RETIRED",
    "Number of mispredicted branches retired",
    {CNTRS12, 0xc5}},
   {"BR_TAKEN_RETIRED",
    "Number of taken branches retired",
    {CNTRS12, 0xc9}},
   {"BR_MISS_PRED_TAKEN_RET",
    "Number of mispredictions branches retired",
    {CNTRS12, 0xca}},
   {"BR_INST_DECODED",
    "Number of branch instructions decoded",
    {CNTRS12, 0xe0}},
   {"BTB_MISSES",
    "Number of branches for which the BTB did not produce a prediction",
    {CNTRS12, 0xe2}},
   {"BR_BOGUS",
    "Number of bogus branches",
    {CNTRS12, 0xe4}},
   {"BACLEARS",
    "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not",
    {CNTRS12, 0xe6}},
   {"RESOURCE_STALLS",
    "Incremented by 1 during every cycle for which there is a resource related stall",
    {CNTRS12, 0xa2}},
   {"PARTIAL_RAT_STALLS",
    "Number of cycles or events for partial stalls.  Includes flag partial stalls",
    {CNTRS12, 0xd2}},
   {"SEGMENT_REG_LOADS",
    "Number of segment register loads",
    {CNTRS12, 0x06}},
   {"CPU_CLK_UNHALTED",
    "Number of cycles during which the processor is not halted, and not in a thermal trip",
    {CNTRS12, 0x79}},
   {"MMX_SAT_INSTR_EXEC",
    "Number of MMX Saturating instructions executed",
    {CNTRS12, 0xb1}},
   {"MMX_UOPS_EXEC",
    "Number of MMX uops executed",
    {CNTRS12, 0xfb2}},
   {"MMX_INSTR_TYPE_EXEC_MUL",
    "Number of MMX packed multiply instructions executed",
    {CNTRS12, 0x1b3}},
   {"MMX_INSTR_TYPE_EXEC_SHIFT",
    "Number of MMX packed shift instructions executed",
    {CNTRS12, 0x2b3}},
   {"MMX_INSTR_TYPE_EXEC_PACK_OPS",
    "Number of MMX pack operation instructions executed",
    {CNTRS12, 0x4b3}},
   {"MMX_INSTR_TYPE_EXEC_UNPACK_OPS",
    "Number of MMX unpack operation instructions executed",
    {CNTRS12, 0x8b3}},
   {"MMX_INSTR_TYPE_EXEC_LOGICAL",
    "Number of MMX packed logical instructions executed",
    {CNTRS12, 0x10b3}},
   {"MMX_INSTR_TYPE_EXEC_ARITHMETIC",
    "Number of MMX packed arithmetic instructions executed",
    {CNTRS12, 0x20b3}},
   {"FP_MMX_TRANS_MMX_TO_FP",
    "Transitions from MMX instruction to floating-point instructions",
    {CNTRS12, 0xcc}},
   {"FP_MMX_TRANS_FP_TO_MMX",
    "Transitions from floating-point instructions to MMX instructions",
    {CNTRS12, 0x1cc}},
   {"MMX_ASSIST",
    "Number of MMX Assists, ie the number of EMMS instructions executed",
    {CNTRS12, 0xcd}},
   {"SEG_RENAME_STALLS_ES",
    "Number of Segment Register ES Renaming stalls",
    {CNTRS12, 0x1d4}},
   {"SEG_RENAME_STALLS_DS",
    "Number of Segment Register DS Renaming stalls",
    {CNTRS12, 0x2d4}},
   {"SEG_RENAME_STALLS_FS",
    "Number of Segment Register FS Renaming stalls",
    {CNTRS12, 0x4d4}},
   {"SEG_RENAME_STALLS_GS",
    "Number of Segment Register GS Renaming stalls",
    {CNTRS12, 0x8d4}},
   {"SEG_RENAME_STALLS_TOT",
    "Total Number of Segment Register Renaming stalls",
    {CNTRS12, 0xfd4}},
   {"SEG_REG_RENAMES_ES",
    "Number of Segment Register ES Renames",
    {CNTRS12, 0x1d5}},
   {"SEG_REG_RENAMES_DS",
    "Number of Segment Register DS Renames",
    {CNTRS12, 0x2d5}},
   {"SEG_REG_RENAMES_FS",
    "Number of Segment Register FS Renames",
    {CNTRS12, 0x4d5}},
   {"SEG_REG_RENAMES_GS",
    "Number of Segment Register GS Renames",
    {CNTRS12, 0x8d5}},
   {"SEG_REG_RENAMES_TOT",
    "Total number of Segment Register Renames",
    {CNTRS12, 0xfd5}},
   {"RET_SEG_RENAMES",
    "Number of segment register rename events retired",
    {CNTRS12, 0xd6}},
   {"", "", {0, 0}}
};

const int _papi_hwd_core_native_count = (PNE_CORE_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_core_native_map[] = {
// 0x40000000
   {"UnhltCore_Cycles",
    "Unhalted core cycles",
    {CNTRS12, 0x3c}},
   {"UnhltRef_Cycles",
    "Unhalted reference cycles, Measures bus cycle",
    {CNTRS12, 0x13c}},
   {"Instr_Retired",
    "Instruction retired",
    {CNTRS12, 0xc0}},
   {"LLC_Reference",
    "LL cache references",
    {CNTRS12, 0x4f2e}},
   {"LLC_Misses",
    "LL cache misses",
    {CNTRS12, 0x412e}},
   {"Br_Retired",
    "Branch instruction retired",
    {CNTRS12, 0xc4}},
   {"MispredBr_Retired",
    "Mispredicted Branch Instruction retired",
    {CNTRS12, 0xc5}},
   {"LD_Blocks",
    "Load operations delayed due to store buffer blocks.",
    {CNTRS12, 0x3}},
   {"SD_Drains",
    "Cycles while draining store buffers",
    {CNTRS12, 0x4}},
   {"Misalign_Mem_Ref",
    "Misaligned data memory references",
    {CNTRS12, 0x5}},
   {"Seg_Reg_Loads",
    "Segment register loads",
    {CNTRS12, 0x6}},
   {"SSE_PrefNta_Ret",
    "SSE software prefetch instruction PREFETCHNTA retired",
    {CNTRS12, 0x7}},
   {"SSE_PrefT1_Ret",
    "SSE software prefetch instruction PREFETCHT1 retired",
    {CNTRS12, 0x107}},
   {"SSE_PrefT2_Ret",
    "SSE software prefetch instruction PREFETCHT2 retired",
    {CNTRS12, 0x207}},
   {"SSE_NTStores_Ret",
    "SSE streaming store instruction retired",
    {CNTRS12, 0x307}},
   {"FP_Comps_Op_Exe",
    "FP computational Instruction executed",
    {CNTRS12, 0x10}},
// 0x40000010
   {"FP_Assist",
    "FP exceptions experienced microcode assists",
    {CNTRS12, 0x11}},
   {"Mul",
    "Multiply operations",
    {CNTRS12, 0x12}},
   {"Div",
    "Divide operations",
    {CNTRS12, 0x13}},
   {"Cycles_Div_Busy",
    "Cycles the divider is busy",
    {CNTRS12, 0x14}},
   {"L2_ADS_Self",
    "L2 Address strobes Require corespecificity",
    {CNTRS12, 0x4021}},
   {"L2_ADS_Both_Cores",
    "L2 Address strobes Require corespecificity",
    {CNTRS12, 0xc021}},
   {"Dbus_Busy_Self",
    "Core cycle during which data bus was busy",
    {CNTRS12, 0x4022}},
   {"Dbus_Busy_Both_Cores",
    "Core cycle during which data bus was busy",
    {CNTRS12, 0xc022}},
   {"Dbus_Busy_Rd_Self",
    "Cycles data bus is busy transferring data to a core",
    {CNTRS12, 0x4023}},
   {"Dbus_Busy_Rd_Both_Cores",
    "Cycles data bus is busy transferring data to a core",
    {CNTRS12, 0xc023}},
   {"L2_Lines_In_Self_Any",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x7024}},
   {"L2_Lines_In_Self_Demand",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x4024}},
   {"L2_Lines_In_Self_Prefetch",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x5024}},
   {"L2_Lines_In_Both_Cores_Any",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xf024}},
   {"L2_Lines_In_Both_Cores_Demand",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xc024}},
   {"L2_Lines_In_Both_Cores_Prefetch",
    "L2 cache lines allocated Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xd024}},
// 0x40000020
   {"L2_M_Lines_In_Self",
    "L2 Modified-state cache lines allocated Require corespecificity",
    {CNTRS12, 0x4025}},
   {"L2_M_Lines_In_Both_Cores",
    "L2 Modified-state cache lines allocated Require corespecificity",
    {CNTRS12, 0xc025}},
   {"L2_Lines_Out_Self_Any",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x7026}},
   {"L2_Lines_Out_Self_Demand",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x4026}},
   {"L2_Lines_Out_Self_Prefetch",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0x5026}},
   {"L2_Lines_Out_Both_Cores_Any",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xf026}},
   {"L2_Lines_Out_Both_Cores_Demand",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xc026}},
   {"L2_Lines_Out_Both_Cores_Prefetch",
    "L2 cache lines evicted Require corespecificity and HW prefetch qualification.",
    {CNTRS12, 0xd026}},
   {"L2_M_Lines_Out_Self_Any",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0x7027}},
   {"L2_M_Lines_Out_Self_Demand",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0x4027}},
   {"L2_M_Lines_Out_Self_Prefetch",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0x5027}},
   {"L2_M_Lines_Out_Both_Cores_Any",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0xf027}},
   {"L2_M_Lines_Out_Both_Cores_Demand",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0xc027}},
   {"L2_M_Lines_Out_Both_Cores_Prefetch",
    "L2 Modified-state cache lines evicted",
    {CNTRS12, 0xd027}},
   {"L2_IFetch_Self",
    "Support MESI qualification L2 instruction fetches from instruction fetch unit",
    {CNTRS12 | HAS_MESI, 0x4028}},
   {"L2_IFetch_Both_Cores",
    "Support MESI qualification L2 instruction fetches from instruction fetch unit",
    {CNTRS12 | HAS_MESI, 0xc028}},
// 0x40000030
   {"L2_LD_Self_Any",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0x7029}},
   {"L2_LD_Self_Demand",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0x4029}},
   {"L2_LD_Self_Prefetch",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0x5029}},
   {"L2_LD_Both_Cores_Any",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0xf029}},
   {"L2_LD_Both_Cores_Demand",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0xc029}},
   {"L2_LD_Both_Cores_Prefetch",
    "Support MESI qualification L2 cache reads Require corespecificity.",
    {CNTRS12 | HAS_MESI, 0xd029}},
   {"L2_ST_Self",
    "Support MESI qualification L2 cache writes",
    {CNTRS12 | HAS_MESI, 0x402a}},
   {"L2_ST_Both_Cores",
    "Support MESI qualification L2 cache writes",
    {CNTRS12 | HAS_MESI, 0xc02a}},
   {"L2_Rqsts_Self_Any",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0x702e}},
   {"L2_Rqsts_Self_Demand",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0x402e}},
   {"L2_Rqsts_Self_Prefetch",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0x502e}},
   {"L2_Rqsts_Both_Cores_Any",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0xf02e}},
   {"L2_Rqsts_Both_Cores_Demand",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0xc02e}},
   {"L2_Rqsts_Both_Cores_Prefetch",
    "Support MESI qualification L2 cache reference requests.",
    {CNTRS12 | HAS_MESI, 0xd02e}},
   {"L2_Reject_Cycles_Self_Any",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0x7030}},
   {"L2_Reject_Cycles_Self_Demand",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0x4030}},
// 0x40000040
   {"L2_Reject_Cycles_Self_Prefetch",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0x5030}},
   {"L2_Reject_Cycles_Both_Cores_Any",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0xf030}},
   {"L2_Reject_Cycles_Both_Cores_Demand",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0xc030}},
   {"L2_Reject_Cycles_Both_Cores_Prefetch",
    "Support MESI qualification Cycles L2 is busy and rejecting new requests",
    {CNTRS12 | HAS_MESI, 0xd030}},
   {"L2_No_Request_Cycles_Self",
    "Support MESI qualification Cycles there is no request to access L2",
    {CNTRS12 | HAS_MESI, 0x4032}},
   {"L2_No_Request_Cycles_Both_Cores",
    "Support MESI qualification Cycles there is no request to access L2",
    {CNTRS12 | HAS_MESI, 0xc032}},
   {"EST_Trans_All",
    "Any Intel Enhanced SpeedStep(R) Technology transitions",
    {CNTRS12, 0x3a}},
   {"EST_Trans_Frequency",
    "Any Intel Enhanced SpeedStep(R) Technology frequency transitions",
    {CNTRS12, 0x103a}},
   {"Thermal_Trip",
    "Duration in a thermal trip based on the current core clock Use Edge trigger to count occurrence",
    {CNTRS12, 0xc03b}},
   {"NonHlt_Ref_Cycles",
    "Non-halted bus cycles",
    {CNTRS12, 0x13c}},
   {"Serial_Execution_Cycles",
    "Non-halted bus cycles of this core executing code while the other core is halted",
    {CNTRS12, 0x23c}},
   {"DCache_Cache_LD",
    "Require MESI qualification L1 cacheable data read operations",
    {CNTRS12 | HAS_MESI, 0x40}},
   {"DCache_Cache_ST",
    "Require MESI qualification L1 cacheable data write operations",
    {CNTRS12 | HAS_MESI, 0x41}},
   {"DCache_Cache_Lock",
    "Require MESI qualification L1 cacheable lock read operations to invalid state",
    {CNTRS12 | HAS_MESI, 0x42}},
   {"Data_Mem_Ref",
    "L1 data read and writes of cacheable and non-cacheable types",
    {CNTRS12, 0x143}},
   {"Data_Mem_Cache_Ref",
    "L1 data cacheable read and write operations",
    {CNTRS12, 0x244}},
// 0x40000050
   {"DCache_Repl",
    "L1 data cache line replacements",
    {CNTRS12, 0xf45}},
   {"DCache_M_Repl",
    "L1 data M-state cache line allocated",
    {CNTRS12, 0x46}},
   {"DCache_M_Evict",
    "L1 data M-state cache line evicted",
    {CNTRS12, 0x47}},
   {"DCache_Pend_Miss",
    "Weighted cycles of L1 miss oustanding Use Cmask =1 to count duration",
    {CNTRS12, 0x48}},
   {"Dtlb_Miss",
    "Data references that missed TLB",
    {CNTRS12, 0x49}},
   {"SSE_PrefNta_Miss",
    "PREFETCHNTA missed all caches",
    {CNTRS12, 0x4b}},
   {"SSE_PrefT1_Miss",
    "PREFETCHT1 missed all caches",
    {CNTRS12, 0x14b}},
   {"SSE_PrefT2_Miss",
    "PREFETCHT2 missed all caches",
    {CNTRS12, 0x24b}},
   {"SSE_NTStores_Miss",
    "SSE streaming store instruction missed all caches",
    {CNTRS12, 0x34b}},
   {"L1_Pref_Req",
    "L1 prefetch requests due to DCU cache misses May overcount if a request was resubmitted",
    {CNTRS12, 0x4f}},
   {"Bus_Req_Outstanding_Self",
    "Require corespecificity, and agent specificity Weighted cycles of cacheable bus data read requests.",
    {CNTRS12, 0x4060}},
   {"Bus_Req_Outstanding_Both_Cores_This_Agent",
    "Require corespecificity, and agent specificity Weighted cycles of cacheable bus data read requests.",
    {CNTRS12, 0xc060}},
   {"Bus_Req_Outstanding_All_Agents",
    "Require corespecificity, and agent specificity Weighted cycles of cacheable bus data read requests.",
    {CNTRS12, 0xe060}},
   {"Bus_BNR_Clocks",
    "External bus cycles while BNR asserted",
    {CNTRS12, 0x61}},
   {"Bus_DRDY_Clocks_This_Agent",
    "External bus cycles while DRDY asserted Require agent specificity",
    {CNTRS12, 0x62}},
   {"Bus_DRDY_Clocks_All_Agents",
    "External bus cycles while DRDY asserted Require agent specificity",
    {CNTRS12, 0x2062}},
// 0x40000060
   {"Bus_Locks_Clocks_Self",
    "External bus cycles while bus lock signal asserted Require core specificity",
    {CNTRS12, 0x4063}},
   {"Bus_Locks_Clocks_Both_Cores_This_Agent",
    "External bus cycles while bus lock signal asserted Require core specificity",
    {CNTRS12, 0xc063}},
   {"Bus_Locks_Clocks_All_Agents",
    "External bus cycles while bus lock signal asserted Require core specificity",
    {CNTRS12, 0xe063}},
   {"Bus_Data_Rcv",
    "External bus cycles while bus lock signal asserted",
    {CNTRS12, 0x4064}},
   {"Bus_Trans_Brd_Self",
    "Burst read bus transactions (data or code) Require core specificity",
    {CNTRS12, 0x4065}},
   {"Bus_Trans_Brd_Both_Cores_This_Agent",
    "Burst read bus transactions (data or code) Require core specificity",
    {CNTRS12, 0xc065}},
   {"Bus_Trans_Brd_All_Agents",
    "Burst read bus transactions (data or code) Require core specificity",
    {CNTRS12, 0xe065}},
   {"Bus_Trans_RFO_Self",
    "Completed read for ownership (RFO) transactions.",
    {CNTRS12, 0x4066}},
   {"Bus_Trans_RFO_Both_Cores_This_Agent",
    "Completed read for ownership (RFO) transactions.",
    {CNTRS12, 0xc066}},
   {"Bus_Trans_RFO_All_Agents",
    "Completed read for ownership (RFO) transactions.",
    {CNTRS12, 0xe066}},
   {"Bus_Trans_Ifetch_Self",
    "Completed instruction fetch transactions.",
    {CNTRS12, 0x4068}},
   {"Bus_Trans_Ifetch_Both_Cores_This_Agent",
    "Completed instruction fetch transactions.",
    {CNTRS12, 0xc068}},
   {"Bus_Trans_Ifetch_All_Agents",
    "Completed instruction fetch transactions.",
    {CNTRS12, 0xe068}},
   {"Bus_Trans_Inval_Self",
    "Completed invalidate transactions.",
    {CNTRS12, 0x4069}},
   {"Bus_Trans_Inval_Both_Cores_This_Agent",
    "Completed invalidate transactions.",
    {CNTRS12, 0xc069}},
   {"Bus_Trans_Inval_All_Agents",
    "Completed invalidate transactions.",
    {CNTRS12, 0xe069}},
// 0x40000070
   {"Bus_Trans_Pwr_Self",
    "Completed partial write transactions.",
    {CNTRS12, 0x406a}},
   {"Bus_Trans_Pwr_Both_Cores_This_Agent",
    "Completed partial write transactions.",
    {CNTRS12, 0xc06a}},
   {"Bus_Trans_Pwr_All_Agents",
    "Completed partial write transactions.",
    {CNTRS12, 0xe06a}},
   {"Bus_Trans_P_Self",
    "Completed partial transactions (include partial read + partial write + line write).",
    {CNTRS12, 0x406b}},
   {"Bus_Trans_P_Both_Cores_This_Agent",
    "Completed partial transactions (include partial read + partial write + line write).",
    {CNTRS12, 0xc06b}},
   {"Bus_Trans_P_All_Agents",
    "Completed partial transactions (include partial read + partial write + line write).",
    {CNTRS12, 0xe06b}},
   {"Bus_Trans_IO_Self",
    "Completed I/O transactions (read and write).",
    {CNTRS12, 0x406c}},
   {"Bus_Trans_IO_Both_Cores_This_Agent",
    "Completed I/O transactions (read and write).",
    {CNTRS12, 0xc06c}},
   {"Bus_Trans_IO_All_Agents",
    "Completed I/O transactions (read and write).",
    {CNTRS12, 0xe06c}},
   {"Bus_Trans_Def",
    "Completed defer transactions.",
    {CNTRS12, 0x206d}},
   {"Bus_Trans_WB",
    "Completed writeback transactions from DCU (does not include L2 writebacks).",
    {CNTRS12, 0xc067}},
   {"Bus_Trans_Burst",
    "Completed burst transactions ( full line transactions include reads, write, RFO, and writebacks).",
    {CNTRS12, 0xc06e}},
   {"Bus_Trans_Mem",
    "Completed memory transactions. This includes Bus_Trans_Burst + Bus_Trans_P + Bus_Trans_Inval.",
    {CNTRS12, 0xc06f}},
   {"Bus_Trans_Any",
    "Any completed bus transactions.",
    {CNTRS12, 0xc070}},
   {"Bus_Snoops",
    "External bus cycles while bus lock signal asserted",
    {CNTRS12, 0x77}},
   {"DCU_Snoop_To_Share",
    "DCU snoops to share-state L1 cache line due to L1 misses",
    {CNTRS12, 0x178}},
// 0x40000080
   {"Bus_Not_In_Use",
    "Number of cycles there is no transaction from the core",
    {CNTRS12, 0x7d}},
   {"Bus_Snoop_Stall",
    "Number of bus cycles while bus snoop is stalled",
    {CNTRS12, 0x7e}},
   {"ICache_Reads",
    "Number of instruction fetches from ICache, streaming buffers (both cacheable and uncacheable fetches)",
    {CNTRS12, 0x80}},
   {"ICache_Misses",
    "Number of instruction fetch misses from ICache, streaming buffers.",
    {CNTRS12, 0x81}},
   {"ITLB_Misses",
    "Number of iITLB misses",
    {CNTRS12, 0x85}},
   {"IFU_Mem_Stall",
    "Cycles IFU is stalled while waiting for data from memory",
    {CNTRS12, 0x86}},
   {"ILD_Stall",
    "Number of instruction length decoder stalls (Counts number of LCP stalls)",
    {CNTRS12, 0x87}},
   {"Br_Inst_Exec",
    "Branch instruction executed (includes speculation)",
    {CNTRS12, 0x88}},
   {"Br_Missp_Exec",
    "Branch instruction executed and were mispredicted at execution (includes branches that do not have prediction or mispredicted)",
    {CNTRS12, 0x89}},
   {"Br_BAC_Missp_Exec",
    "Branch instruction executed that were mispredicted at front end..",
    {CNTRS12, 0x8a}},
   {"Br_Cnd_Exec",
    "Conditional branch instruction executed.",
    {CNTRS12, 0x8b}},
   {"Br_Cnd_Missp_Exec",
    "Conditional branch instruction executed that were mispredicted",
    {CNTRS12, 0x8c}},
   {"Br_Ind_Exec",
    "Indirect branch instruction executed.",
    {CNTRS12, 0x8d}},
   {"Br_Ind_Missp_Exec",
    "Indirect branch instruction executed that were mispredicted",
    {CNTRS12, 0x8e}},
   {"Br_Ret_Exec",
    "Return branch instruction executed.",
    {CNTRS12, 0x8f}},
   {"Br_Ret_Missp_Exec",
    "Return branch instruction executed that were mispredicted.",
    {CNTRS12, 0x90}},
// 0x40000090
   {"Br_Ret_BAC_Missp_Exec",
    "Return branch instruction executed that were mispredicted at the Front End.",
    {CNTRS12, 0x91}},
   {"Br_Call_Exec",
    "Return call instruction executed.",
    {CNTRS12, 0x92}},
   {"Br_Call_Missp_Exec",
    "Return call instruction executed that were mispredicted.",
    {CNTRS12, 0x93}},
   {"Br_Ind_Call_Exec",
    "Indirect call branch instruction executed.",
    {CNTRS12, 0x94}},
   {"Resource_Stall",
    "Cycles while there is a resource related stall (renaming, buffer entries) as seen by allocator.",
    {CNTRS12, 0xa2}},
   {"MMX_Instr_Exec",
    "Number of MMX instruction executed (does not include MOVQ and MOVD stores).",
    {CNTRS12, 0xb0}},
   {"SIMD_Int_Sat_Exec",
    "Number of SIMD Integer saturating instruction executed.",
    {CNTRS12, 0xb1}},
   {"SIMD_Int_Pmul_Exec",
    "Number of SIMD Integer packed multiply instruction executed.",
    {CNTRS12, 0x1b3}},
   {"SIMD_Int_Psft_Exec",
    "Number of SIMD Integer packed shift instruction executed.",
    {CNTRS12, 0x2b3}},
   {"SIMD_Int_Pck_Exec",
    "Number of SIMD Integer pack operation instruction executed.",
    {CNTRS12, 0x4b3}},
   {"SIMD_Int_Upck_Exec",
    "Number of SIMD Integer unpack instruction executed.",
    {CNTRS12, 0x8b3}},
   {"SIMD_Int_Plog_Exec",
    "Number of SIMD Integer packed logical instruction executed.",
    {CNTRS12, 0x10b3}},
   {"SIMD_Int_Pari_Exec",
    "Number of SIMD Integer packed arithmetic instruction executed.",
    {CNTRS12, 0x20b3}},
   {"Instr_Ret",
    "Number of instruction retired (Macro fused instruction count as 2).",
    {CNTRS12, 0xc0}},
   {"FP_Comp_Instr_Ret",
    "Number of FP compute instruction retired (X87 instruction or instruction that contain X87 operations).",
    {CNTRS12, 0xc1}},
   {"Uops_Ret",
    "Number of micro-ops retired (include fused uops).",
    {CNTRS12, 0xc2}},
// 0x400000A0
   {"SMC_Detected",
    "Number of times self-modifying code condition is detected.",
    {CNTRS12, 0xc3}},
   {"Br_Instr_Ret",
    "Number of branch instruction retired",
    {CNTRS12, 0xc4}},
   {"Br_MisPred_Ret",
    "Number of mispredicted branch instruction retired",
    {CNTRS12, 0xc5}},
   {"Cycles_Int_Masked",
    "Cycles while interrupt is disabled.",
    {CNTRS12, 0xc6}},
   {"Cycles_Int_Pedning_Masked",
    "Cycles while interrupt is disabled and interrupts are pending.",
    {CNTRS12, 0xc7}},
   {"HW_Int_Rx",
    "Number of hardware interrupts received.",
    {CNTRS12, 0xc8}},
   {"Br_Taken_Ret",
    "Number of taken branch instruction retired.",
    {CNTRS12, 0xc9}},
   {"Br_MisPred_Taken_Ret",
    "Number of taken and mispredicted branch instruction retired.",
    {CNTRS12, 0xca}},
   {"MMX_FP_Trans",
    "Number of transitions From MMX to X87.",
    {CNTRS12, 0xcc}},
   {"FP_MMX_Trans",
    "Number of transitions From X87 to MMX.",
    {CNTRS12, 0x1cc}},
   {"MMX_Assist",
    "Number of EMMS executed.",
    {CNTRS12, 0xcd}},
   {"MMX_Instr_Ret",
    "Number of MMX instruction retired.",
    {CNTRS12, 0xce}},
   {"Instr_Decoded",
    "Number of instruction decoded.",
    {CNTRS12, 0xd0}},
   {"ESP_Uops",
    "Number of ESP folding instruction decoded.",
    {CNTRS12, 0xd7}},
   {"SIMD_FP_SP_Ret",
    "Number of SSE/SSE2 single precision instructions retired (packed and scalar).",
    {CNTRS12, 0xd8}},
   {"SIMD_FP_SP_S_Ret",
    "Number of SSE/SSE2 scalar single precision instructions retired.",
    {CNTRS12, 0x1d8}},
// 0x400000B0
   {"SIMD_FP_DP_P_Ret",
    "Number of SSE/SSE2 packed double precision instructions retired.",
    {CNTRS12, 0x2d8}},
   {"SIMD_FP_DP_S_Ret",
    "Number of SSE/SSE2 scalar double precision instructions retired.",
    {CNTRS12, 0x3d8}},
   {"SIMD_Int_128_Ret",
    "Number of SSE2 128 bit integer instructions retired.",
    {CNTRS12, 0x4d8}},
   {"SIMD_FP_SP_P_Comp_Ret",
    "Number of SSE/SSE2 packed single precision compute instructions retired (does not include AND, OR, XOR).",
    {CNTRS12, 0xd9}},
   {"SIMD_FP_SP_S_Comp_Ret",
    "Number of SSE/SSE2 scalar single precision compute instructions retired (does not include AND, OR, XOR).",
    {CNTRS12, 0x1d9}},
   {"SIMD_FP_DP_P_Comp_Ret",
    "Number of SSE/SSE2 packed double precision compute instructions retired (does not include AND, OR, XOR).",
    {CNTRS12, 0x2d9}},
   {"SIMD_FP_DP_S_Comp_Ret",
    "Number of SSE/SSE2 scalar double precision compute instructions retired (does not include AND, OR, XOR).",
    {CNTRS12, 0x3d9}},
   {"Fused_Uops_Ret",
    "All fused uops retired.",
    {CNTRS12, 0xda}},
   {"Fused_Ld_Uops_Ret",
    "Fused load uops retired.",
    {CNTRS12, 0x1da}},
   {"Fused_St_Uops_Ret",
    "Fused store uops retired.",
    {CNTRS12, 0x2da}},
   {"Unfusion",
    "Number of unfusion events in the ROB (due to exception).",
    {CNTRS12, 0xdb}},
   {"Br_Instr_Decoded",
    "Branch instruction decoded.",
    {CNTRS12, 0xe0}},
   {"BTB_Misses",
    "Number of branches the BTB did not produce a prediction",
    {CNTRS12, 0xe2}},
   {"Br_Bogus",
    "Number of bogus branches",
    {CNTRS12, 0xe4}},
   {"BAClears",
    "Number of BAClears asserted",
    {CNTRS12, 0xe6}},
   {"Pref_Rqsts_Up",
    "Number of hardware prefetch request issued in forward streams",
    {CNTRS12, 0xf0}},
// 0x400000C0
   {"Pref_Rqsts_Dn",
    "Number of hardware prefetch request issued in backward streams",
    {CNTRS12, 0xf8}},
   {"", "", {0, 0}}
};

const int _papi_hwd_p2_native_count = (PNE_P2_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_p2_native_map[] = {
   {"DATA_MEM_REFS",
    "All loads/stores from/to any memory type",
    {CNTRS12, 0x43}},
   {"DCU_LINES_IN",
    "Total lines allocated in the DCU",
    {CNTRS12, 0x45}},
   {"DCU_M_LINES_IN",
    "Number of M state lines allocated in the DCU",
    {CNTRS12, 0x46}},
   {"DCU_M_LINES_OUT",
    "Number of M state lines evicted from the DCU",
    {CNTRS12, 0x47}},
   {"DCU_MISS_OUTSTANDING",
    "Weighted no. of cycles while a DCU miss is outstanding, incremented by the no. of outstanding cache misses at any particular time",
    {CNTRS12, 0x48}},
   {"IFU_IFETCH",
    "Number of instruction fetches, both cacheable and noncacheable, including UC fetches",
    {CNTRS12, 0x80}},
   {"IFU_IFETCH_MISS",
    "Number of instruction fetch misses including UC accesses",
    {CNTRS12, 0x81}},
   {"ITLB_MISS",
    "Number of ITLB misses",
    {CNTRS12, 0x85}},
   {"IFU_MEM_STALL",
    "Number of cycles instruction fetch is stalled, for any reason, including IFU cache misses, ITLB misses, ITLB faults, and other minor stalls",
    {CNTRS12, 0x86}},
   {"ILD_STALL",
    "Number of cycles the instruction length decoder is stalled",
    {CNTRS12, 0x87}},

   {"L2_IFETCH",
    "Number of fetches from a line of L2 instruction cache",
    {CNTRS12 | HAS_MESI, 0x28}},
   {"L2_LD",
    "Number of loads from a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x29}},
   {"L2_ST",
    "Number of stores to a line of the L2 data cache",
    {CNTRS12 | HAS_MESI, 0x2a}},
   {"L2_RQSTS",
    "Total number of L2 requests to a line",
    {CNTRS12 | HAS_MESI, 0x2e}},

   {"L2_LINES_IN",
    "Number of lines allocated in the L2",
    {CNTRS12, 0x24}},
   {"L2_LINES_OUT",
    "Number of lines removed fromo the L2 for any reason",
    {CNTRS12, 0x26}},
   {"L2_M_LINES_INM",
    "Number of modified lines allocated in the L2",
    {CNTRS12, 0x25}},
   {"L2_M_LINES_OUTM",
    "Number of modified lines removed from the L2 for any reason",
    {CNTRS12, 0x27}},
   {"L2_ADS",
    "Number of L2 address strobes",
    {CNTRS12, 0x21}},
   {"L2_DBS_BUSY",
    "Number of cycles the L2 cache data bus was busy",
    {CNTRS12, 0x22}},
   {"L2_DBS_BUSY_RD",
    "Number of cycles the data bus was busy transferring read data from the L2 to the processor",
    {CNTRS12, 0x23}},
   {"BUS_DRDY_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving DRDY#",
    {CNTRS12, 0x62}},
   {"BUS_DRDY_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving DRDY#",
    {CNTRS12, 0x2062}},
   {"BUS_LOCK_CLOCKS_SELF",
    "Number of clock cycles during which the processor is driving LOCK#",
    {CNTRS12, 0x63}},
   {"BUS_LOCK_CLOCKS_ANY",
    "Number of clock cycles during which any agent is driving LOCK#",
    {CNTRS12, 0x2063}},
   {"BUS_REQ_OUTSTANDING",
    "Number of bus outstanding bus requests",
    {CNTRS12, 0x60}},
   {"BUS_TRAN_BRD_SELF",
    "Number of burst read transactions by the processor",
    {CNTRS12, 0x65}},
   {"BUS_TRAN_BRD_ANY",
    "Number of burst read transactions by any agent",
    {CNTRS12, 0x2065}},
   {"BUS_TRAN_RFO_SELF",
    "Number of completed read for ownership transactions by the processor",
    {CNTRS12, 0x66}},
   {"BUS_TRAN_RFO_ANY",
    "Number of completed read for ownership transactions by any agent",
    {CNTRS12, 0x2066}},
   {"BUS_TRANS_WB_SELF",
    "Number of completed write back transactions by the processor",
    {CNTRS12, 0x67}},
   {"BUS_TRANS_WB_ANY",
    "Number of completed write back transactions by any agent",
    {CNTRS12, 0x2067}},
   {"BUS_TRAN_IFETCH_SELF",
    "Number of completed instruction fetch transactions by the processor",
    {CNTRS12, 0x68}},
   {"BUS_TRAN_IFETCH_ANY",
    "Number of completed instruction fetch transactions by any agent",
    {CNTRS12, 0x2068}},
   {"BUS_TRAN_INVAL_SELF",
    "Number of completed invalidate transactions by the processor",
    {CNTRS12, 0x69}},
   {"BUS_TRAN_INVAL_ANY",
    "Number of completed invalidate transactions by any agent",
    {CNTRS12, 0x2069}},
   {"BUS_TRAN_PWR_SELF",
    "Number of completed partial write transactions by the processor",
    {CNTRS12, 0x6a}},
   {"BUS_TRAN_PWR_ANY",
    "Number of completed partial write transactions by any agent",
    {CNTRS12, 0x206a}},
   {"BUS_TRANS_P_SELF",
    "Number of completed partial transactions by the processor",
    {CNTRS12, 0x6b}},
   {"BUS_TRANS_P_ANY",
    "Number of completed partial transactions by any agent",
    {CNTRS12, 0x206b}},
   {"BUS_TRANS_IO_SELF",
    "Number of completed I/O transactions by the processor",
    {CNTRS12, 0x6c}},
   {"BUS_TRANS_IO_ANY",
    "Number of completed I/O transactions by any agent",
    {CNTRS12, 0x206c}},
   {"BUS_TRAN_DEF_SELF",
    "Number of completed deferred transactions by the processor",
    {CNTRS12, 0x6d}},
   {"BUS_TRAN_DEF_ANY",
    "Number of completed deferred transactions by any agent",
    {CNTRS12, 0x206d}},
   {"BUS_TRAN_BURST_SELF",
    "Number of completed burst transactions by the processor",
    {CNTRS12, 0x6e}},
   {"BUS_TRAN_BURST_ANY",
    "Number of completed burst transactions by any agent",
    {CNTRS12, 0x206e}},
   {"BUS_TRAN_ANY_SELF",
    "Number of completed bus transactions by the processor",
    {CNTRS12, 0x70}},
   {"BUS_TRAN_ANY_ANY",
    "Number of completed bus transactions by any agent",
    {CNTRS12, 0x2070}},
   {"BUS_TRAN_MEM_SELF",
    "Number of completed memory transactions by the processor",
    {CNTRS12, 0x6f}},
   {"BUS_TRAN_MEM_ANY",
    "Number of completed memory transactions by any agent",
    {CNTRS12, 0x206f}},
   {"BUS_DATA_RCV",
    "Number of bus clock cycles during which this processor is receiving data",
    {CNTRS12, 0x64}},
   {"BUS_BNR_DRV",
    "Number of bus clock cycles during which this processor is driving the BNR# pin",
    {CNTRS12, 0x61}},
   {"BUS_HIT_DRV",
    "Number of bus clock cycles during which this processor is driving the HIT# pin",
    {CNTRS12, 0x7a}},
   {"BUS_HITM_DRV",
    "Number of bus clock cycles during which this processor is driving the HITM# pin",
    {CNTRS12, 0x7b}},
   {"BUS_SNOOP_STALL",
    "Number of clock cycles during which the bus is snoop stalled",
    {CNTRS12, 0x7e}},
   {"FLOPS",
    "Number of computational floating-point operations retired",
    {CNTR1, 0xc1}},
   {"FP_COMP_OPS_EXE",
    "Number of computational floating-point operations executed",
    {CNTR1, 0x10}},
   {"FP_ASSIST",
    "Number of floating-point exception cases handled by microcode",
    {CNTR2, 0x11}},
   {"MUL",
    "Number of integer and floating point multiplies",
    {CNTR2, 0x12}},
   {"DIV",
    "Number of integer and floating point divides",
    {CNTR2, 0x13}},
   {"CYCLES_DIV_BUSY",
    "Number of cycles during which the divider is busy and cannot accept new divides",
    {CNTR1, 0x14}},
   {"LD_BLOCKS",
    "Number of load operations delayed due to store buffer blocks",
    {CNTRS12, 0x3}},
   {"SB_DRAINS",
    "Number of store buffer drain cycles",
    {CNTRS12, 0x4}},
   {"MISALIGN_MEM_REF",
    "Number of misaligned data memory references",
    {CNTRS12, 0x5}},
   {"INST_RETIRED",
    "Number of instructions retired",
    {CNTRS12, 0xc0}},
   {"UOPS_RETIRED",
    "Number of uops retired",
    {CNTRS12, 0xc2}},
   {"INST_DECODED",
    "Number of instructions decoded",
    {CNTRS12, 0xd0}},
   {"HW_INT_RX",
    "Number of hardware interrupts received",
    {CNTRS12, 0xc8}},
   {"CYCLES_INT_MASKED",
    "Number of processor cycles to which interrupts are enabled",
    {CNTRS12, 0xc6}},
   {"CYCLES_INT_PENDING_AND_MASKED",
    "Number of processor cycles for which interrupts are disabled and interrupts are pending",
    {CNTRS12, 0xc7}},
   {"BR_INST_RETIRED",
    "Number of branch instructions retired",
    {CNTRS12, 0xc4}},
   {"BR_MISS_PRED_RETIRED",
    "Number of mispredicted branches retired",
    {CNTRS12, 0xc5}},
   {"BR_TAKEN_RETIRED",
    "Number of taken branches retired",
    {CNTRS12, 0xc9}},
   {"BR_MISS_PRED_TAKEN_RET",
    "Number of mispredictions branches retired",
    {CNTRS12, 0xca}},
   {"BR_INST_DECODED",
    "Number of branch instructions decoded",
    {CNTRS12, 0xe0}},
   {"BTB_MISSES",
    "Number of branches for which the BTB did not produce a prediction",
    {CNTRS12, 0xe2}},
   {"BR_BOGUS",
    "Number of bogus branches",
    {CNTRS12, 0xe4}},
   {"BACLEARS",
    "Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not",
    {CNTRS12, 0xe6}},
   {"RESOURCE_STALLS",
    "Incremented by 1 during every cycle for which there is a resource related stall",
    {CNTRS12, 0xa2}},
   {"PARTIAL_RAT_STALLS",
    "Number of cycles or events for partial stalls.  Includes flag partial stalls",
    {CNTRS12, 0xd2}},
   {"SEGMENT_REG_LOADS",
    "Number of segment register loads",
    {CNTRS12, 0x06}},
   {"CPU_CLK_UNHALTED",
    "Number of cycles during which the processor is not halted",
    {CNTRS12, 0x79}},
   {"MMX_INSTR_EXEC",
    "Number of MMX instructions executed",
    {CNTRS12, 0xb0}},
   {"MMX_SAT_INSTR_EXEC",
    "Number of MMX Saturating instructions executed",
    {CNTRS12, 0xb1}},
   {"MMX_UOPS_EXEC",
    "Number of MMX uops executed",
    {CNTRS12, 0xfb2}},
   {"MMX_INSTR_TYPE_EXEC_MUL",
    "Number of MMX packed multiply instructions executed",
    {CNTRS12, 0x1b3}},
   {"MMX_INSTR_TYPE_EXEC_SHIFT",
    "Number of MMX packed shift instructions executed",
    {CNTRS12, 0x2b3}},
   {"MMX_INSTR_TYPE_EXEC_PACK_OPS",
    "Number of MMX pack operation instructions executed",
    {CNTRS12, 0x4b3}},
   {"MMX_INSTR_TYPE_EXEC_UNPACK_OPS",
    "Number of MMX unpack operation instructions executed",
    {CNTRS12, 0x8b3}},
   {"MMX_INSTR_TYPE_EXEC_LOGICAL",
    "Number of MMX packed logical instructions executed",
    {CNTRS12, 0x10b3}},
   {"MMX_INSTR_TYPE_EXEC_ARITHMETIC",
    "Number of MMX packed arithmetic instructions executed",
    {CNTRS12, 0x20b3}},
   {"FP_MMX_TRANS_MMX_TO_FP",
    "Transitions from MMX instruction to floating-point instructions",
    {CNTRS12, 0xcc}},
   {"FP_MMX_TRANS_FP_TO_MMX",
    "Transitions from floating-point instructions to MMX instructions",
    {CNTRS12, 0x1cc}},
   {"MMX_ASSIST",
    "Number of MMX Assists, ie the number of EMMS instructions executed",
    {CNTRS12, 0xcd}},
   {"MMX_INSTR_RET",
    "Number of MMX instructions retired",
    {CNTRS12, 0xce}},
   {"SEG_RENAME_STALLS_ES",
    "Number of Segment Register ES Renaming stalls",
    {CNTRS12, 0x1d4}},
   {"SEG_RENAME_STALLS_DS",
    "Number of Segment Register DS Renaming stalls",
    {CNTRS12, 0x2d4}},
   {"SEG_RENAME_STALLS_FS",
    "Number of Segment Register FS Renaming stalls",
    {CNTRS12, 0x4d4}},
   {"SEG_RENAME_STALLS_GS",
    "Number of Segment Register GS Renaming stalls",
    {CNTRS12, 0x8d4}},
   {"SEG_RENAME_STALLS_TOT",
    "Total Number of Segment Register Renaming stalls",
    {CNTRS12, 0xfd4}},
   {"SEG_REG_RENAMES_ES",
    "Number of Segment Register ES Renames",
    {CNTRS12, 0x1d5}},
   {"SEG_REG_RENAMES_DS",
    "Number of Segment Register DS Renames",
    {CNTRS12, 0x2d5}},
   {"SEG_REG_RENAMES_FS",
    "Number of Segment Register FS Renames",
    {CNTRS12, 0x4d5}},
   {"SEG_REG_RENAMES_GS",
    "Number of Segment Register GS Renames",
    {CNTRS12, 0x8d5}},
   {"SEG_REG_RENAMES_TOT",
    "Total number of Segment Register Renames",
    {CNTRS12, 0xfd5}},
   {"RET_SEG_RENAMES",
    "Number of segment register rename events retired",
    {CNTRS12, 0xd6}},
   {"", "", {0, 0}}
};

const int _papi_hwd_k7_native_count = (PNE_ATH_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_k7_native_map[] = {
   {"SEG_REG_LOADS",
    "Number of segment register loads",
    {ALLCNTRS, 0x20}},
   {"ST_ACTIVE_IS",
    "Number of stores to active instruction stream (self-modifying code occurences)",
    {ALLCNTRS, 0x21}},
   {"DC_ACCESSES",
    "Number of data cache accesses",
    {ALLCNTRS, 0x40}},
   {"DC_MISSES",
    "Number of data cache misses",
    {ALLCNTRS, 0x41}},

   {"L2_DC_REFILLS",
    "Number of data cache lines refilled from L2",
    {ALLCNTRS | HAS_MOESI, 0x42}},
   {"SYS_DC_REFILLS",
    "Number of data cache lines refilled from system",
    {ALLCNTRS | HAS_MOESI, 0x43}},
   {"DC_WB",
    "Number of data cache writebacks",
    {ALLCNTRS | HAS_MOESI, 0x44}},

   {"L1_DTLB_MISSES ANDL2_DTLB_HITS",
    "L1 DTLB misses and L2 DLTB hits",
    {ALLCNTRS, 0x45}},
   {"L1_AND_L2_DTLB_MISSES",
    "L1 and L2 DTLB misses",
    {ALLCNTRS, 0x46}},
   {"MISALIGNED_DATA_REFERENCES",
    "Misaligned data references",
    {ALLCNTRS, 0x47}},
   {"DRAM_SYS_REQS",
    "Number of DRAM system requests",
    {ALLCNTRS, 0x64}},
   {"SYS_REQS_SEL_TYPE",
    "Number of system request with the selected type", /* ??? */
    {ALLCNTRS, 0x65}},
   {"SNOOP_HITS",
    "Number of snoop hits",
    {ALLCNTRS, 0x73}},
   {"ECC_ERR",
    "Number of single bit ecc errors detected or corrected",
    {ALLCNTRS, 0x74}},
   {"INTERNAL_CACHE_INV",
    "Number of internal cache line invalidates",
    {ALLCNTRS, 0x75}},
   {"TOT_CYC",
    "Number of cycles processor is running",
    {ALLCNTRS, 0x76}},
   {"L2_REQ",
    "Number of L2 requests",
    {ALLCNTRS, 0x79}},
   {"FILL_REQ_STALLS",
    "Number of cycles that at least one fill request waited to use the L2",
    {ALLCNTRS, 0x7a}},
   {"IC_FETCHES",
    "Number of instruction cache fetches",
    {ALLCNTRS, 0x80}},
   {"IC_MISSES",
    "Number of instruction cache misses",
    {ALLCNTRS, 0x81}},
   {"L2_IC_REFILLS",
    "Number of instruction cache refills from L2",
    {ALLCNTRS, 0x82}},
   {"SYS_IC_REFILLS",
    "Number of instruction cache refills from system",
    {ALLCNTRS, 0x83}},
   {"L1_ITLB_MISSES",
    "Number of L1 ITLB misses (and L2 ITLB hits.)",
    {ALLCNTRS, 0x84}},
   {"L2_ITLB_MISSES",
    "Number of (L1 and) L2 ITLB misses",
    {ALLCNTRS, 0x85}},
   {"SNOOP_RESYNCS",
    "Number of snoop resyncs",
    {ALLCNTRS, 0x86}},
   {"IFETCH_STALLS",
    "Number of instruction fetch stall cycles",
    {ALLCNTRS, 0x87}},
   {"RET_STACK_HITS",
    "Number of return stack hits",
    {ALLCNTRS, 0x88}},
   {"RET_STACK_OVERFLOW",
    "Return stack overflow",
    {ALLCNTRS, 0x89}},
   {"RET_INSTRUCTIONS",
    "Retired instructions (includes exceptions, interrupts, resyncs.)",
    {ALLCNTRS, 0xc0}},
   {"RET_OPS",
    "Retired ops",
    {ALLCNTRS, 0xc1}},
   {"RET_BR",
    "Retired branches (conditional, unconditional, exceptions, interrupts.)",
    {ALLCNTRS, 0xc2}},
   {"RET_BR_MIS",
    "Retired branches mispredicted",
    {ALLCNTRS, 0xc3}},
   {"RET_TAKEN_BR",
    "Retired taken branches",
    {ALLCNTRS, 0xc4}},
   {"RET_TAKEN_BR_MIS",
    "Retired taken branches mispredicted",
    {ALLCNTRS, 0xc5}},
   {"RET_FAR_CONTROL_TRANSFERS",
    "Retired far control transfers",
    {ALLCNTRS, 0xc6}},
   {"RET_RESYNC_BR",
    "Retired resync branches - only non-control transfer branches counted",
    {ALLCNTRS, 0xc7}},
   {"RET_NEAR_RETURNS",
    "Retired near returns",
    {ALLCNTRS, 0xc8}},
   {"RET_NEAR_RETURNS_MIS",
    "Retired near returns mispredicted",
    {ALLCNTRS, 0xc9}},
   {"RET_INDIRECT_BR_MIS",
    "Retired indirect branches with target mispredicted",
    {ALLCNTRS, 0xca}},
   {"INTS_MASKED_CYC",
    "Interrupts masked cycles (IF=0)",
    {ALLCNTRS, 0xcd}},
   {"INTS_MASKED_WHILE_PENDING_CYC",
    "Interrupts masked while pending cycles (INTR while IF=0)",
    {ALLCNTRS, 0xce}},
   {"TAKEN_HARDWARE_INTS",
    "Number of taken hardware interrupts",
    {ALLCNTRS, 0xcf}},
   {"INS_DECODER_EMPTY",
    "Number of cycles in whih the instruction decoder is empty",
    {ALLCNTRS, 0xd0}},
   {"DISPATCH_STALLS",
    "Number of dispatch stalls",
    {ALLCNTRS, 0xd1}},
   {"BRANCH_ABORTS",
    "Number of branch aborts to retire",
    {ALLCNTRS, 0xd2}},
   {"SERIALIZE",
    "Serialize",
    {ALLCNTRS, 0xd3}},
   {"SEG_LOAD_STALLS",
    "Number of segment load stalls",
    {ALLCNTRS, 0xd4}},
   {"ICU_FULL",
    "Number of cycles in which the ICU is full",
    {ALLCNTRS, 0xd5}},
   {"RES_STATIONS_FULL",
    "Number of cycles in which the reservation station is full",
    {ALLCNTRS, 0xd6}},
   {"FPU_FULL",
    "Number of cycles in which the FPU is full",
    {ALLCNTRS, 0xd7}},
   {"LS_FULL",
    "Number of cycles in which the LS is full",
    {ALLCNTRS, 0xd8}},
   {"ALL_QUIET_STALL",
    "Number of all quiet stalls",
    {ALLCNTRS, 0xd9}},
   {"TRANS_OR_BRANCH_PENDING",
    "Far transfer or resync branch pending",
    {ALLCNTRS, 0xda}},
   {"BP_DR0",
    "Number of breakpoint matches for DR0",
    {ALLCNTRS, 0xdc}},
   {"BP_DR1",
    "Number of breakpoint matches for DR1",
    {ALLCNTRS, 0xdd}},
   {"BP_DR2",
    "Number of breakpoint matches for DR2",
    {ALLCNTRS, 0xde}},
   {"BP_DR3",
    "Number of breakpoint matches for DR3",
    {ALLCNTRS, 0xdf}},
   {"", "", {0, 0}}
};

/* The first two letters in each entry indicate to which unit
   the event refers. */

const int _papi_hwd_k8_native_count = (PNE_OPT_LAST_NATIVE_EVENT & PAPI_NATIVE_AND_MASK);
const native_event_entry_t _papi_hwd_k8_native_map[] = {
   {"FP_ADD_PIPE",
    "Dispatched FPU ops - Revision B and later - Speculative add pipe ops",
    {ALLCNTRS, 0x0100}},
   {"FP_MULT_PIPE",
    "Dispatched FPU ops - Revision B and later - Speculative multiply pipe ops",
    {ALLCNTRS, 0x0200}},
   {"FP_MULT_AND_ADD_PIPE",
    "Dispatched FPU ops - Revision B and later - Speculative multiply and add pipe ops",
    {ALLCNTRS, 0x0300}},
   {"FP_ST_PIPE",
    "Dispatched FPU ops - Revision B and later - Store pipe ops",
    {ALLCNTRS, 0x0400}},
   {"FP_ADD_PIPE_LOAD",
    "Dispatched FPU ops - Revision B and later - Add pipe load ops",
    {ALLCNTRS, 0x0800}},
   {"FP_MULT_PIPE_LOAD",
    "Dispatched FPU ops - Revision B and later - Multiply pipe load ops",
    {ALLCNTRS, 0x1000}},
   {"FP_ST_PIPE_LOAD",
    "Dispatched FPU ops - Revision B and later - Store pipe load ops",
    {ALLCNTRS, 0x2000}},
   {"FP_ST_PIPE_AND_LOAD",
    "Dispatched FPU ops - Revision B and later - Store pipe ops and load ops",
    {ALLCNTRS, 0x2400}},
   {"FP_NONE_RET",
    "Cycles with no FPU ops retired - Revision B and later",
    {ALLCNTRS, 0x01}},
   {"FP_FAST_FLAG",
    "Dispatched FPU ops that use the fast flag interface - Revision B and later",
    {ALLCNTRS, 0x02}},
   {"LS_SEG_REG_LOADS_ES",
    "Number of segment register loads - ES",
    {ALLCNTRS, 0x0120}},
   {"LS_SEG_REG_LOADS_CS",
    "Number of segment register loads - CS",
    {ALLCNTRS, 0x0220}},
   {"LS_SEG_REG_LOADS_SS",
    "Number of segment register loads - SS",
    {ALLCNTRS, 0x0420}},
   {"LS_SEG_REG_LOADS_DS",
    "Number of segment register loads - DS",
    {ALLCNTRS, 0x0820}},
   {"LS_SEG_REG_LOADS_FS",
    "Number of segment register loads - FS",
    {ALLCNTRS, 0x1020}},
   {"LS_SEG_REG_LOADS_GS",
    "Number of segment register loads - GS",
    {ALLCNTRS, 0x2020}},
   {"LS_SEG_REG_LOADS_HS",
    "Number of segment register loads - HS",
    {ALLCNTRS, 0x4020}},
   {"LS_SELF_MODIFYING_RESYNC",
    "Microarchitectural resync caused by self-modifying code",
    {ALLCNTRS, 0x21}},
   {"LS_SNOOP_RESYNC",
    "Microarchitectural resync caused by snoop",
    {ALLCNTRS, 0x22}},
   {"LS_BUF_2_FULL",
    "LS buffer 2 full",
    {ALLCNTRS, 0x23}},
   {"LS_LOCK_INS",
    "Locked operation - Revision B and earlier versions - Number of lock instructions executed - Revision C and later revisions",
    {ALLCNTRS, 0x124}},
   {"LS_LOCK_REQ",
    "Locked operation - Revision B and earlier versions - Number of cycles spent in the lock request or grant stage - Revision C and later revisions",
    {ALLCNTRS, 0x224}},
   {"LS_LOCK_COMP",
    "Locked operation - Revision B and earlier versions - Number of cycles a lock takes to complete once it is non-speculative and is the oldest load or store operation - non-speculative cycles in Ls2 entry 0- Revision C and later revisions",
    {ALLCNTRS, 0x424}},
   {"LS_LATE_CANCEL",
    "Microarchitectural late cancel of an operation",
    {ALLCNTRS, 0x25}},
   {"LS_CFLUSH",
    "Retired CFLUSH instructions",
    {ALLCNTRS, 0x26}},
   {"LS_CPUID",
    "Retired CPUID instructions",
    {ALLCNTRS, 0x27}},
   {"MEM_RQ_UC",
    "Requests to non-cacheable (UC) memory",
    {ALLCNTRS, 0x0165}},
   {"MEM_RQ_WC",
    "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
    {ALLCNTRS, 0x0265}},
   {"MEM_RQ_SS",
    "Streaming store (SS) requests",
    {ALLCNTRS, 0x8065}},
   {"DC_ACCESS", 
    "Access - includes microcode scratchpad accesses",
    {ALLCNTRS, 0x40}},
   {"DC_MISS",
    "Miss",
    {ALLCNTRS, 0x41}},
   {"DC_L2_REFILL",
    "Refill from L2",
    {ALLCNTRS | HAS_MOESI, 0x42}},
   {"DC_SYS_REFILL",
    "Refill from system",
    {ALLCNTRS | HAS_MOESI, 0x43}},
   {"DC_COPYBACK",
    "Copyback",
    {ALLCNTRS | HAS_MOESI, 0x44}},
   {"DC_L1_DTLB_MISS_AND_L2_DTLB_HIT",
    "L1 DTLB miss and L2 DTLB hit",
    {ALLCNTRS, 0x45}},
   {"DC_L1_DTLB_MISS_AND_L2_DTLB_MISS",
    "L1 DTLB miss and L2 DTLB miss",
    {ALLCNTRS, 0x46}},
   {"DC_MISALIGNED_DATA_REF",
    "Misaligned data reference",
    {ALLCNTRS, 0x47}},
   {"DC_LATE_CANCEL",
    "Microarchitectural late cancel of an access",
    {ALLCNTRS, 0x48}},
   {"DC_EARLY_CANCEL",
    "Microarchitectural early cancel of an access",
    {ALLCNTRS, 0x49}},
   {"DC_ECC_SCRUBBER_ERR",
    "One bit ECC error recorded found by scrubber - Scrubber error",
    {ALLCNTRS, 0x14a}},
   {"DC_ECC_PIGGY_SCRUBBER_ERR",
    "One bit ECC error recorded found by scrubber - Piggyback scrubber errors",
    {ALLCNTRS, 0x24a}},
   {"DC_DISPATCHED_PREFETCH_LOAD",
    "Dispatched prefetch instructions - Load",
    {ALLCNTRS, 0x14b}},
   {"DC_DISPATCHED_PREFETCH_STORE",
    "Dispatched prefetch instructions - Store",
    {ALLCNTRS, 0x24b}},
   {"DC_DISPATCHED_PREFETCH_NTA",
    "Dispatched prefetch instructions - NTA",
    {ALLCNTRS, 0x44b}},
   {"DC_ACCESSES_BY_LOCK",
    "DCACHE accesses by locks - Revision C and later revisions - Number of dcache accesses by lock instructions",
    {ALLCNTRS, 0x14c}},
   {"DC_MISSES_BY_LOCK",
    "DCACHE accesses by locks - Revision C and later revisions - Number of dcache misses by lock instructions",
    {ALLCNTRS, 0x24c}},
   {"SI_PREFETCH_CANCEL",
    "Data prefetcher request cancelled",
    {ALLCNTRS, 0x167}},
   {"SI_PREFETCH_ATTEMPT",
    "Data prefetcher request attempted",
    {ALLCNTRS, 0x267}},
   {"SI_RD_RESP_EXCL",
    "Responses from the system for exclusive cache refill requests",
    {ALLCNTRS, 0x16c}},
   {"SI_RD_RESP_MOD",
    "Responses from the system for modified cache refill requests",
    {ALLCNTRS, 0x26c}},
   {"SI_RD_RESP_SHR",
    "Responses from the system for shared cache refill requests",
    {ALLCNTRS, 0x46c}},
   {"BU_L2_REQ_IC",
    "Internal L2 request - IC fill",
    {ALLCNTRS, 0x17d}},
   {"BU_L2_REQ_DC",
    "Internal L2 request - DC fill",
    {ALLCNTRS, 0x27d}},
   {"BU_L2_REQ_TLB_RELOAD",
    "Internal L2 request - TLB reload",
    {ALLCNTRS, 0x47d}},
   {"BU_L2_REQ_TAG_SNOOP_REQ",
    "Internal L2 request - Tag snoop request",
    {ALLCNTRS, 0x87d}},
   {"BU_L2_REQ_CANC_REQ",
    "Internal L2 request - Cancelled request",
    {ALLCNTRS, 0x107d}},
   {"BU_L2_FILL_MISS_IC",
    "Fill request that missed in L2 - IC fill",
    {ALLCNTRS, 0x17e}},
   {"BU_L2_FILL_MISS_DC",
    "Fill request that missed in L2 - DC fill",
    {ALLCNTRS, 0x27e}},
   {"BU_L2_FILL_MISS_TLB_RELOAD",
    "Fill request that missed in L2 - TLB reload",
    {ALLCNTRS, 0x47e}},
   {"BU_L2_FILL_DIRTY",
    "Fill into L2 - Dirty L2 victim",
    {ALLCNTRS, 0x17f}},
   {"BU_L2_FILL_FROM_L1",
    "Fill into L2 - Victim from L1",
    {ALLCNTRS, 0x27f}},
   {"IC_FETCH",
    "Fetch",
    {ALLCNTRS, 0x80}},
   {"IC_MISS",
    "Miss",
    {ALLCNTRS, 0x81}},
   {"IC_L2_REFILL",
    "Refill from L2",
    {ALLCNTRS, 0x82}},
   {"IC_SYS_REFILL",
    "Refill from system",
    {ALLCNTRS, 0x83}},
   {"IC_L1ITLB_MISS_AND_L2ITLB_HIT",
    "L1ITLB miss and L2ITLB hit",
    {ALLCNTRS, 0x84}},
   {"IC_L1ITLB_MISS_AND_L2ITLB_MISS",
    "L1ITLB miss and L2ITLB miss",
    {ALLCNTRS, 0x85}},
   {"IC_RESYNC",
    "Microarchitectural resync caused by snoop",
    {ALLCNTRS, 0x86}},
   {"IC_FETCH_STALL",
    "Instruction fetch stall",
    {ALLCNTRS, 0x87}},
   {"IC_STACK_HIT",
    "Return stack hit",
    {ALLCNTRS, 0x88}},
   {"IC_STACK_OVERFLOW",
    "Return stack overflow",
    {ALLCNTRS, 0x89}},
   {"FR_X86_INS",
    "Retired x86 instructions including exceptions and interrupts",
    {ALLCNTRS, 0xC0}},
   {"FR_RET_UOPS",
    "Retired uops",
    {ALLCNTRS, 0xC1}},
   {"FR_BR",
    "Retired branches including exceptions and interrupts",
    {ALLCNTRS, 0xC2}},
   {"FR_BR_MIS",
    "Retired branches mispredicted",
    {ALLCNTRS, 0xC3}},
   {"FR_BR_TAKEN",
    "Retired taken branches",
    {ALLCNTRS, 0xC4}},
   {"FR_BR_TAKEN_MIS",
    "Retired taken branches mispredicted",
    {ALLCNTRS, 0xC5}},
   {"FR_FAR_CONTROL_TRANSFERS",
    "Retired far control transfers - always mispredicted",
    {ALLCNTRS, 0xC6}},
   {"FR_RESYNCS",
    "Retired resyncs - non control transfer branches",
    {ALLCNTRS, 0xC7}},
   {"FR_NEAR_RETURNS",
    "Retired near returns",
    {ALLCNTRS, 0xC8}},
   {"FR_NEAR_RETURNS_MIS",
    "Retired near returns mispredicted",
    {ALLCNTRS, 0xC9}},
   {"FR_BR_MISCOMPARE",
    "Retired taken branches mispredicted only due to address miscompare",
    {ALLCNTRS, 0xCa}},
   {"FR_FPU_X87",
    "Retired FPU instructions - Revision B and later - x87 instructions",
    {ALLCNTRS, 0x1Cb}},
   {"FR_FPU_MMX_3D",
    "Retired FPU instructions - Revision B and later - Combined MMX and 3DNow! instructions",
    {ALLCNTRS, 0x2Cb}},
   {"FR_FPU_SSE_SSE2_PACKED",
    "Retired FPU instructions - Revision B and later - Combined packed SSE and SSE2 instructions",
    {ALLCNTRS, 0x4Cb}},
   {"FR_FPU_SSE_SSE2_SCALAR",
    "Retired FPU instructions - Revision B and later - Combined scalar SSE and SSE2 instructions",
    {ALLCNTRS, 0x8Cb}},
   {"FR_FPU_X87_SSE_SSE2_SCALAR",
    "Retired FPU instructions - Revision B and later - Combined x87, scalar SSE and SSE2 instructions",
    {ALLCNTRS, 0x9Cb}},
   {"FR_FPU_X87_SSE_SSE2_SCALAR_PACKED",
    "Retired FPU instructions - Revision B and later - Combined x87, scalar & packed SSE and SSE2 instructions",
    {ALLCNTRS, 0xDCb}},
   {"FR_FASTPATH_POS0",
    "Retired fastpath double op instructions - Revision B and later revisions - With low op in position 0",
    {ALLCNTRS, 0x1Cc}},
   {"FR_FASTPATH_POS1",
    "Retired fastpath double op instructions - Revision B and later revisions - With low op in position 1",
    {ALLCNTRS, 0x2Cc}},
   {"FR_FASTPATH_POS2",
    "Retired fastpath double op instructions - Revision B and later revisions - With low op in position 2",
    {ALLCNTRS, 0x4Cc}},
   {"FR_INTS_MASKED",
    "Interrupts masked cycles - IF=0",
    {ALLCNTRS, 0xCd}},
   {"FR_INTS_MASKED_PENDING",
    "Interrupts masked while pending cycles - INTR while IF=0",
    {ALLCNTRS, 0xCe}},
   {"FR_HW_INTS",
    "Taken hardware interrupts",
    {ALLCNTRS, 0xCf}},
   {"FR_DECODER_EMPTY",
    "Nothing to dispatch - decoder empty",
    {ALLCNTRS, 0xD0}},
   {"FR_DISPATCH_STALLS",
    "Dispatch stalls - D2h or DAh combined",
    {ALLCNTRS, 0xD1}},
   {"FR_DISPATCH_STALLS_BR",
    "Dispatch stall from branch abort to retire",
    {ALLCNTRS, 0xD2}},
   {"FR_DISPATCH_STALLS_SER",
    "Dispatch stall for serialization",
    {ALLCNTRS, 0xD3}},
   {"FR_DISPATCH_STALLS_SEG",
    "Dispatch stall for segment load",
    {ALLCNTRS, 0xD4}},
   {"FR_DISPATCH_STALLS_FULL_REORDER",
    "Dispatch stall when reorder buffer is full",
    {ALLCNTRS, 0xD5}},
   {"FR_DISPATCH_STALLS_FULL_RESERVATION",
    "Dispatch stall when reservation stations are full",
    {ALLCNTRS, 0xD6}},
   {"FR_DISPATCH_STALLS_FULL_FPU",
    "Dispatch stall when FPU is full",
    {ALLCNTRS, 0xD7}},
   {"FR_DISPATCH_STALLS_FULL_LS",
    "Dispatch stall when LS is full",
    {ALLCNTRS, 0xD8}},
   {"FR_DISPATCH_STALLS_QUIET",
    "Dispatch stall when waiting for all to be quiet",
    {ALLCNTRS, 0xD9}},
   {"FR_DISPATCH_STALLS_FAR",
    "Dispatch stall when far control transfer or resync branch is pending",
    {ALLCNTRS, 0xDa}},
   {"FR_FPU_EXCEPTIONS_X87",
    "FPU exceptions - Revision B and later revisions - x87 reclass microfaults",
    {ALLCNTRS, 0x1Db}},
   {"FR_FPU_EXCEPTIONS_SSE_RETYPE",
    "FPU exceptions - Revision B and later revisions - SSE retype microfaults",
    {ALLCNTRS, 0x2Db}},
   {"FR_FPU_EXCEPTIONS_SSE_RECLASS",
    "FPU exceptions - Revision B and later revisions - SSE reclass microfaults",
    {ALLCNTRS, 0x4Db}},
   {"FR_FPU_EXCEPTIONS_SSE_MICROTRAPS",
    "FPU exceptions - Revision B and later revisions - SSE and x87 microtraps",
    {ALLCNTRS, 0x8Db}},
   {"FR_BP_DR0",
    "Number of breakpoints for DR0",
    {ALLCNTRS, 0xDc}},
   {"FR_BP_DR1",
    "Number of breakpoints for DR1",
    {ALLCNTRS, 0xDd}},
   {"FR_BP_DR2",
    "Number of breakpoints for DR2",
    {ALLCNTRS, 0xDe}},
   {"FR_BP_DR3",
    "Number of breakpoints for DR3",
    {ALLCNTRS, 0xDf}},
   {"NB_MC_PAGE_HIT",
    "Memory controller page access event - Page hit",
    {ALLCNTRS, 0x1E0}},
   {"NB_MC_PAGE_MISS",
    "Memory controller page access event - Page miss",
    {ALLCNTRS, 0x2E0}},
   {"NB_MC_PAGE_CONFLICT",
    "Memory controller page access event - Page conflict",
    {ALLCNTRS, 0x4E0}},
   {"NB_MC_PAGE_TBL_OVERFLOW",
    "Memory controller page table overflow",
    {ALLCNTRS, 0xE1}},
   {"NB_MC_DRAM",
    "Memory controller DRAM command slots missed - in MemClks",
    {ALLCNTRS, 0xE2}},
   {"NB_MC_TURNAROUND_DIMM",
    "Memory controller turnaround - DIMM turnaround",
    {ALLCNTRS, 0x1E3}},
   {"NB_MC_TURNAROUND_RTW",
    "Memory controller turnaround - Read to write turnaround",
    {ALLCNTRS, 0x2E3}},
   {"NB_MC_TURNAROUND_WTR",
    "Memory controller turnaround - Write to read turnaround",
    {ALLCNTRS, 0x4E3}},
   {"NB_MC_BYPASS_HP",
    "Memory controller bypass counter saturation - high priority",
    {ALLCNTRS, 0x1E4}},
   {"NB_MC_BYPASS_LP",
    "Memory controller bypass counter saturation - low priority",
    {ALLCNTRS, 0x2E4}},
   {"NB_MC_BYPASS_INTERFACE",
    "Memory controller bypass counter saturation - DRAM controller interface bypass",
    {ALLCNTRS, 0x4E4}},
   {"NB_MC_BYPASS_QUEUE",
    "Memory controller bypass counter saturation - DRAM controller queue bypass",
    {ALLCNTRS, 0x8E4}},
   {"NB_SIZED_NONPOSTWRSZBYTE",
    "Sized commands - NonPostWrSzByte",
    {ALLCNTRS, 0x1Eb}},
   {"NB_SIZED_NONPOSTWRSZDWORD",
    "Sized commands - NonPostWrSzDword",
    {ALLCNTRS, 0x2Eb}},
   {"NB_SIZED_POSTWRSZBYTE",
    "Sized commands - PostWrSzByte",
    {ALLCNTRS, 0x4Eb}},
   {"NB_SIZED_POSTWRSZDWORD",
    "Sized commands - PostWrSzDword",
    {ALLCNTRS, 0x8Eb}},
   {"NB_SIZED_RDSZBYTE",
    "Sized commands - RdSzByte",
    {ALLCNTRS, 0x10Eb}},
   {"NB_SIZED_RDSZDWORD",
    "Sized commands - RdSzDword",
    {ALLCNTRS, 0x20Eb}},
   {"NB_SIZED_RDMODWR",
    "Sized commands - RdModWr",
    {ALLCNTRS, 0x40Eb}},
   {"NB_PROBE_MISS",
    "Probe result - Probe miss",
    {ALLCNTRS, 0x1Ec}},
   {"NB_PROBE_HIT",
    "Probe result - Probe Hit",
    {ALLCNTRS, 0x2Ec}},
   {"NB_PROBE_HIT_DIRTY_NO_MEM_CANCEL",
    "Probe result - Probe hit dirty without memory cancel",
    {ALLCNTRS, 0x4Ec}},
   {"NB_PROBE_HIT_DIRTY_MEM_CANCEL",
    "Probe result - Probe hit dirty with memory cancel",
    {ALLCNTRS, 0x8Ec}},
   {"NB_HT_BUS0_COMMAND",
    "HyperTransport bus 0 bandwidth - Command sent",
    {ALLCNTRS, 0x1F6}},
   {"NB_HT_BUS0_DATA",
    "HyperTransport bus 0 bandwidth - Data sent",
    {ALLCNTRS, 0x2F6}},
   {"NB_HT_BUS0_BUFF",
    "HyperTransport bus 0 bandwidth - Buffer release sent",
    {ALLCNTRS, 0x4F6}},
   {"NB_HT_BUS0_NOP",
    "HyperTransport bus 0 bandwidth - Nop sent",
    {ALLCNTRS, 0x8F6}},
   {"NB_HT_BUS1_COMMAND",
    "HyperTransport bus 1 bandwidth - Command sent",
    {ALLCNTRS, 0x1F7}},
   {"NB_HT_BUS1_DATA",
    "HyperTransport bus 1 bandwidth - Data sent",
    {ALLCNTRS, 0x2F7}},
   {"NB_HT_BUS1_BUFF",
    "HyperTransport bus 1 bandwidth - Buffer release sent",
    {ALLCNTRS, 0x4F7}},
   {"NB_HT_BUS1_NOP",
    "HyperTransport bus 1 bandwidth - Nop sent",
    {ALLCNTRS, 0x8F7}},
   {"NB_HT_BUS2_COMMAND",
    "HyperTransport bus 2 bandwidth - Command sent",
    {ALLCNTRS, 0x1F8}},
   {"NB_HT_BUS2_DATA",
    "HyperTransport bus 2 bandwidth - Data sent",
    {ALLCNTRS, 0x2F8}},
   {"NB_HT_BUS2_BUFF",
    "HyperTransport bus 2 bandwidth - Buffer release sent",
    {ALLCNTRS, 0x4F8}},
   {"NB_HT_BUS2_NOP",
    "HyperTransport bus 2 bandwidth - Nop sent",
    {ALLCNTRS, 0x8F8}},
   {"CPU_CLK_UNHALTED",
    "Cycles processor is running (not in HLT or STPCLK state)",
    {ALLCNTRS, 0x76}},
   {"HT_LL_MEM_XFR",
    "HyperTransport data transfer from local memory to local memory",
    {ALLCNTRS, 0x43a8e9}},
   {"HT_LR_MEM_XFR",
    "HyperTransport data transfer from local memory to remote memory",
    {ALLCNTRS, 0x4398e9}},
   {"HT_RL_MEM_XFR",
    "HyperTransport data transfer from remote memory to local memory",
    {ALLCNTRS, 0x4368e9}},
   {"HT_LL_IO_XFR",
    "HyperTransport data transfer from local memory to local IO",
    {ALLCNTRS, 0x43a4e9}},
   {"HT_LR_IO_XFR",
    "HyperTransport data transfer from local memory to remote IO",
    {ALLCNTRS, 0x4394e9}},
   {"HT_RL_IO_XFR",
    "HyperTransport data transfer from remote memory to local IO",
    {ALLCNTRS, 0x43a8e9}},
   {"", "", {0, 0}}
};

/*************************************/
/* CODE TO SUPPORT OPAQUE NATIVE MAP */
/*************************************/

/* **NOT THREAD SAFE STATIC!!**
   The name and description strings below are both declared static. 
   This is NOT thread-safe, because these values are returned 
     for use by the calling program, and could be trashed by another thread
     before they are used. To prevent this, any call to routines using these
     variables (_papi_hwd_code_to_{name,descr}) should be wrapped in 
     _papi_hwi_{lock,unlock} calls.
   They are declared static to reserve non-volatile space for constructed strings.
*/
static char name[128];
static char description[1024];

inline_static void internal_decode_event(unsigned int EventCode, int *event, int *moesi)
{
   /* mask off the native event flag and the MOESI bits */
   *event = (EventCode & PAPI_NATIVE_AND_MASK) & (~MOESI_ALL);
   /* find the moesi bits (if any) */
   *moesi = (EventCode & MOESI_ALL);
}

/* Called by _papi_hwd_ntv_code_to_{name,descr}() to build the return strings.
   See above for discussion of name and description strings.
*/
static char *internal_translate_code(int event, int moesi, char *str, char *separator)
{
   if (*separator == '_') /* implied flag for name */
      strcpy(str, native_table[event].name);
   else
      strcpy(str, native_table[event].description);

   // do a sanity check for valid mask bits
   if (!moesi)
      return (str);
   if ((moesi & MOESI_ALL) != moesi)
      return (NULL);

   strcat(str, separator);
   if (*separator == '_') { /* implied flag for name */
      if (moesi & MOESI_M) strcat(str, "M");
      if (moesi & MOESI_O) {
         if (native_table[event].resources.selector & HAS_MOESI) strcat(str, "O");
         else strcat(str, "M");
      }
      if (moesi & MOESI_E) strcat(str, "E");
      if (moesi & MOESI_S) strcat(str, "S");
      if (moesi & MOESI_I) strcat(str, "I");
   }
   else {
      if (moesi & MOESI_M) strcat(str, " Modified");
      if (moesi & MOESI_O) {
         if (native_table[event].resources.selector & HAS_MOESI) strcat(str, " Owner");
         else strcat(str, " Modified");
      }
      if (moesi & MOESI_E) strcat(str, " Exclusive");
      if (moesi & MOESI_S) strcat(str, " Shared");
      if (moesi & MOESI_I) strcat(str, " Invalid");
   }
   return (str);
}


/* Given a native event code, returns the short text label. */
char *_papi_hwd_ntv_code_to_name(unsigned int EventCode)
{
   int event, moesi;

   internal_decode_event(EventCode, &event, &moesi);
   if (event > _papi_hwi_system_info.sub_info.num_native_events) {
       return ('\0'); // return a null string for invalid events
   }

   if (!moesi)
      return (native_table[event].name);
   else {
      return (internal_translate_code(event, moesi, name, "_"));
   }
}

/* Given a native event code, returns the longer native event
   description. */
char *_papi_hwd_ntv_code_to_descr(unsigned int EventCode)
{
   int event, moesi;

   internal_decode_event(EventCode, &event, &moesi);
   if (event > _papi_hwi_system_info.sub_info.num_native_events)
       return ('\0'); // return a null string for invalid events

   if (!moesi)
      return (native_table[event].description);
   else {
      return (internal_translate_code(event, moesi, description, ". Cache bits:"));
   }
}

/* Given a native event code, assigns the native event's 
   information to a given pointer.
   NOTE: the info must be COPIED to the provided pointer,
   not just referenced!
*/
int _papi_hwd_ntv_code_to_bits(unsigned int EventCode, hwd_register_t * bits)
{
   int event, moesi;

   internal_decode_event(EventCode, &event, &moesi);
   if (event > _papi_hwi_system_info.sub_info.num_native_events)
       return (PAPI_ENOEVNT);

   if(native_table[event].resources.selector == 0) {
      return (PAPI_ENOEVNT);
   }
   *bits = native_table[event].resources;
   bits->counter_cmd |= moesi; /* OR MOESI bits into command */
   return (PAPI_OK);
}

/* Given a native event code, looks for next MOESI bit if applicable.
   If not, looks for the next event in the table if the next one exists. 
   If not, returns the proper error code. */
int _papi_hwd_ntv_enum_events(unsigned int *EventCode, int modifier)
{
   int event, moesi;

   internal_decode_event(*EventCode, &event, &moesi);
   if (event > _papi_hwi_system_info.sub_info.num_native_events)
       return (PAPI_ENOEVNT);

   moesi += MOESI_I; /* increment by smallest step size */

   /* for AMD processors, 5 bits are valid */
   if (native_table[event].resources.selector & HAS_MOESI) {
      if (moesi <= MOESI_ALL) {
         *EventCode = (event | PAPI_NATIVE_MASK) + moesi;
         return (PAPI_OK);
      }
   }
   /* for Intel processors, only 4 bits are valid */
   else if (native_table[event].resources.selector & HAS_MESI) {
      if (!(moesi & MOESI_M)) { /* never set top bit */
         *EventCode = (event | PAPI_NATIVE_MASK) + moesi;
         return (PAPI_OK);
      }
   }
   if (native_table[event + 1].resources.selector) {
      *EventCode = (event | PAPI_NATIVE_MASK) + 1;
      return (PAPI_OK);
   } else {
      return (PAPI_ENOEVNT);
   }
}

/* Reports the elements of the hwd_register_t struct as an array of names and a matching array of values.
   Maximum string length is name_len; Maximum number of values is count.
*/
static void copy_value(unsigned int val, char *nam, char *names, unsigned int *values, int len)
{
   *values = val;
   strncpy(names, nam, len);
   names[len-1] = 0;
}

int _papi_hwd_ntv_bits_to_info(hwd_register_t *bits, char *names,
                               unsigned int *values, int name_len, int count)
{
   int i = 0;
   copy_value(bits->selector, "Event Mask", &names[i*name_len], &values[i], name_len);
   if (++i == count) return(i);
   copy_value(bits->counter_cmd, "Event Code", &names[i*name_len], &values[i], name_len);
   return(++i);
}



#define FP_NONE 0
#define  FP_RETIRED 1
#define  FP_SPECULATIVE 2
#define   FP_SP 3
#define   FP_DP 4
void _papi_hwd_fixup_fp(hwi_search_t **s, const hwi_dev_notes_t **n)
{
   char *str = getenv("PAPI_OPTERON_FP");
   int mask = FP_NONE;

   /* if the env variable isn't set, return the defaults */
   if ((str == NULL) || (strlen(str) == 0)) {
      *s = FPU;
      *n = FPU_DESC;
      return;
   }

   if (strstr(str,"RETIRED"))    mask = FP_RETIRED;
   if (strstr(str,"SPECULATIVE"))    mask = FP_SPECULATIVE;
   if (strstr(str,"SSE_SP")) mask =  FP_SP;
   if (strstr(str,"SSE_DP")) mask =  FP_DP;

   switch (mask) {
     case FP_RETIRED:
        *s = _papi_hwd_opt_FP_RETIRED;
        *n = _papi_hwd_opt_FP_RETIRED_dev_notes;
        break;
     case FP_SPECULATIVE:
        *s = _papi_hwd_opt_FP_SPECULATIVE;
        *n = _papi_hwd_opt_FP_SPECULATIVE_dev_notes;
        break;
     case FP_SP:
        *s = _papi_hwd_opt_FP_SSE_SP;
        *n = _papi_hwd_opt_FP_SSE_SP_dev_notes;
        break;
     case FP_DP:
        *s = _papi_hwd_opt_FP_SSE_DP;
        *n = _papi_hwd_opt_FP_SSE_DP_dev_notes;
        break;
     default:
        PAPIERROR("Improper usage of PAPI_OPTERON_FP environment variable");
        PAPIERROR("Use one of RETIRED,SPECULATIVE,SSE_SP,SSE_DP");
        *s = NULL;
        *n = NULL;
   }
}
